| Message ID | 1431452293-16697-2-git-send-email-jonathar@broadcom.com |
|---|---|
| State | Needs Review / ACK, archived |
| Headers | show |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | total: 1 errors, 0 warnings, 0 lines checked |
| robh/patch-applied | success |
On 12/05/15 10:38, Jonathan Richardson wrote: > > Signed-off-by: Jonathan Richardson <jonathar@broadcom.com> > --- > .../devicetree/bindings/spi/brcm,mspi-spi.txt | 39 ++++++++++++++++++++ > 1 file changed, 39 insertions(+) > create mode 100644 Documentation/devicetree/bindings/spi/brcm,mspi-spi.txt > > diff --git a/Documentation/devicetree/bindings/spi/brcm,mspi-spi.txt b/Documentation/devicetree/bindings/spi/brcm,mspi-spi.txt > new file mode 100644 > index 0000000..e86a7a0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/spi/brcm,mspi-spi.txt > @@ -0,0 +1,39 @@ > +Broadcom MSPI controller > + > +The Broadcom MSPI controller is a SPI controller found on various chips such > +as Cygnus. > + > +Required properties: > +- compatible: Must be "brcm,mspi-v0". > + > +- reg: The first register is the physical base address of the MSPI controller. > + The second register is the address of the MSPI interrupt control registers. It > + is only required for chips that have a separate register set for extended > + interrupt control. This is required for Cygnus. In which case we would want to mandate the use of a "reg-names" property, because there could be other kinds of controllers, such as the one found on BCM7xxx where we have the 3 "reg" units, the first one is the MSPI controller register range, while the two others are used for the Boot SPI portion of the controller to accelerate flash reads, so completely unrelated here. Right now, using your driver on this Device Tree/configuration makes bcm_mspi request the second register range and mistakenly assuming this is the extended interrupt control register. You could argue that the BSPI portion should be a separate node, but even so, better be safe than sorry.
diff --git a/Documentation/devicetree/bindings/spi/brcm,mspi-spi.txt b/Documentation/devicetree/bindings/spi/brcm,mspi-spi.txt new file mode 100644 index 0000000..e86a7a0 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/brcm,mspi-spi.txt @@ -0,0 +1,39 @@ +Broadcom MSPI controller + +The Broadcom MSPI controller is a SPI controller found on various chips such +as Cygnus. + +Required properties: +- compatible: Must be "brcm,mspi-v0". + +- reg: The first register is the physical base address of the MSPI controller. + The second register is the address of the MSPI interrupt control registers. It + is only required for chips that have a separate register set for extended + interrupt control. This is required for Cygnus. + +- interrupts: Interrupt ID of the controller. + +Optional properties: +- clocks: The MSPI reference clock. If not provided then it is assumed a clock + is enabled by default and no control of clock-frequency (see below) is + possible. + +- clock-names: The name of the reference clock. + +- clock-frequency: Desired frequency of the clock. This will set the serial + clock baud rate (SPBR) based on the reference clock frequency. The frequency + of the SPBR is mspi_clk / (2 * SPBR) where SPBR is a value between 1-255 + determined by the desired 'clock-frequency'. If not provided then the default + baud rate of the controller is used. + +Example: + +mspi: mspi@18047200 { + compatible = "brcm,mspi-v0"; + reg = <0x18047200 0x188>, + <0x180473a0 0x1c>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&axi41_clk>; + clock-names = "mspi_clk"; + clock-frequency = <12500000>; +};
Signed-off-by: Jonathan Richardson <jonathar@broadcom.com> --- .../devicetree/bindings/spi/brcm,mspi-spi.txt | 39 ++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/brcm,mspi-spi.txt