diff mbox

[v5,15/21] clk: tegra: pll: Add dyn_ramp callback

Message ID 1431451444-23155-17-git-send-email-rklein@nvidia.com
State Superseded, archived
Headers show

Commit Message

Rhyland Klein May 12, 2015, 5:23 p.m. UTC
From: Bill Huang <bilhuang@nvidia.com>

Add a callback to the pll_params for custom dynamic ramping
functions which can be specified per PLL.

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
---
 drivers/clk/tegra/clk.h |    4 ++++
 1 file changed, 4 insertions(+)

Comments

Benson Leung May 13, 2015, 10:20 p.m. UTC | #1
On Tue, May 12, 2015 at 10:23 AM, Rhyland Klein <rklein@nvidia.com> wrote:
> From: Bill Huang <bilhuang@nvidia.com>
>
> Add a callback to the pll_params for custom dynamic ramping
> functions which can be specified per PLL.
>
> Signed-off-by: Bill Huang <bilhuang@nvidia.com>

Modulo kerneldoc addition,
Reviewed-by: Benson Leung <bleung@chromium.org>

> ---
>  drivers/clk/tegra/clk.h |    4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 330729a822cf..a61d388364b3 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -160,6 +160,8 @@ struct div_nmp {
>
>  #define MAX_PLL_MISC_REG_COUNT 6
>
> +struct tegra_clk_pll;
> +
>  /**
>   * struct tegra_clk_pll_params - PLL parameters
>   *
> @@ -271,6 +273,8 @@ struct tegra_clk_pll_params {
>                         unsigned long rate, unsigned long parent_rate);
>         unsigned long   (*adjust_vco)(struct tegra_clk_pll_params *pll_params,
>                                 unsigned long parent_rate);
> +       int     (*dyn_ramp)(struct tegra_clk_pll *pll,
> +                       struct tegra_clk_pll_freq_table *cfg);

Please add kerneldoc for dyn_ramp member above.

>  };
>
>  #define TEGRA_PLL_USE_LOCK BIT(0)
> --
> 1.7.9.5
>
> --
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diff mbox

Patch

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 330729a822cf..a61d388364b3 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -160,6 +160,8 @@  struct div_nmp {
 
 #define MAX_PLL_MISC_REG_COUNT	6
 
+struct tegra_clk_pll;
+
 /**
  * struct tegra_clk_pll_params - PLL parameters
  *
@@ -271,6 +273,8 @@  struct tegra_clk_pll_params {
 			unsigned long rate, unsigned long parent_rate);
 	unsigned long	(*adjust_vco)(struct tegra_clk_pll_params *pll_params,
 				unsigned long parent_rate);
+	int	(*dyn_ramp)(struct tegra_clk_pll *pll,
+			struct tegra_clk_pll_freq_table *cfg);
 };
 
 #define TEGRA_PLL_USE_LOCK BIT(0)