diff mbox

[v5,17/21] clk: tegra: pll: Add logic for SS

Message ID 1431451444-23155-19-git-send-email-rklein@nvidia.com
State Superseded, archived
Headers show

Commit Message

Rhyland Klein May 12, 2015, 5:24 p.m. UTC 
From: Bill Huang <bilhuang@nvidia.com>

Add some logic for Spread Spectrum control. It is used in conjuncture
with SDM fractional dividers. SSC has to be disabled when we configure
the divider settings.

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
---
v5:
  - Reorderd Patch so set_defaults logic is present already

 drivers/clk/tegra/clk-pll.c |   25 ++++++++++++++++++++++++-
 drivers/clk/tegra/clk.h     |    4 ++++
 2 files changed, 28 insertions(+), 1 deletion(-)

Comments

Benson Leung May 14, 2015, 12:25 a.m. UTC | #1 
On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein <rklein@nvidia.com> wrote:
> +static void pll_clk_start_ss(struct tegra_clk_pll *pll)
> +{
> +       if (pll->params->defaults_set && pll->params->ssc_ctrl_en_mask) {

Is there any reason you're checking for the existence of
ssc_ctrl_en_mask rather than ssc_ctrl_reg?

> +               u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
> +
> +               val |= pll->params->ssc_ctrl_en_mask;
> +               pll_writel(val, pll->params->ssc_ctrl_reg, pll);
> +       }
> +}
> +
> +static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
> +{
> +       if (pll->params->defaults_set && pll->params->ssc_ctrl_en_mask) {
> +               u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
> +
> +               val &= ~pll->params->ssc_ctrl_en_mask;
> +               pll_writel(val, pll->params->ssc_ctrl_reg, pll);
> +       }
> +}
> +
Rhyland Klein May 20, 2015, 5:19 p.m. UTC | #2 
On 5/13/2015 8:25 PM, Benson Leung wrote:
> On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein <rklein@nvidia.com> wrote:
>> +static void pll_clk_start_ss(struct tegra_clk_pll *pll)
>> +{
>> +       if (pll->params->defaults_set && pll->params->ssc_ctrl_en_mask) {
> 
> Is there any reason you're checking for the existence of
> ssc_ctrl_en_mask rather than ssc_ctrl_reg?

Not particularly, just a way of seeing if ssc is supported by this pll,
I will change it to check the register to be more consistent with other
checks in the code.

-rhyland
diff mbox

Patch

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 36aa2a95fac0..727fedff824d 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -648,6 +648,26 @@  static void _update_pll_cpcon(struct tegra_clk_pll *pll,
 	pll_writel_misc(val, pll);
 }
 
+static void pll_clk_start_ss(struct tegra_clk_pll *pll)
+{
+	if (pll->params->defaults_set && pll->params->ssc_ctrl_en_mask) {
+		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
+
+		val |= pll->params->ssc_ctrl_en_mask;
+		pll_writel(val, pll->params->ssc_ctrl_reg, pll);
+	}
+}
+
+static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
+{
+	if (pll->params->defaults_set && pll->params->ssc_ctrl_en_mask) {
+		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
+
+		val &= ~pll->params->ssc_ctrl_en_mask;
+		pll_writel(val, pll->params->ssc_ctrl_reg, pll);
+	}
+}
+
 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 			unsigned long rate)
 {
@@ -666,8 +686,10 @@  static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 			return 0;
 	}
 
-	if (state)
+	if (state) {
+		pll_clk_stop_ss(pll);
 		_clk_pll_disable(hw);
+	}
 
 	if (!pll->params->defaults_set && pll->params->set_defaults)
 		pll->params->set_defaults(pll);
@@ -680,6 +702,7 @@  static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 	if (state) {
 		_clk_pll_enable(hw);
 		ret = clk_pll_wait_for_lock(pll);
+		pll_clk_start_ss(pll);
 	}
 
 	return ret;
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 38b4c95cfb2f..32ce32a056ca 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -184,6 +184,8 @@  struct tegra_clk_pll;
  * @sdm_din_mask:		Mask of SDM divider bits
  * @sdm_ctrl_reg:		Register offset where SDM enable is
  * @sdm_ctrl_en_mask:		Mask of SDM enable bit
+ * @ssc_ctrl_reg:		Register offset where SSC settings are
+ * @ssc_ctrl_en_mask:		Mask of SSC enable bit
  * @aux_reg:			AUX register offset
  * @dyn_ramp_reg:		Dynamic ramp control register offset
  * @ext_misc_reg:		Miscellaneous control register offsets
@@ -251,6 +253,8 @@  struct tegra_clk_pll_params {
 	u32		sdm_din_mask;
 	u32		sdm_ctrl_reg;
 	u32		sdm_ctrl_en_mask;
+	u32		ssc_ctrl_reg;
+	u32		ssc_ctrl_en_mask;
 	u32		aux_reg;
 	u32		dyn_ramp_reg;
 	u32		ext_misc_reg[MAX_PLL_MISC_REG_COUNT];