From patchwork Fri Mar 5 20:43:41 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Kleikamp X-Patchwork-Id: 47024 X-Patchwork-Delegate: jwboyer@gmail.com Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from bilbo.ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id C302EB7E1D for ; Sat, 6 Mar 2010 07:45:14 +1100 (EST) Received: by ozlabs.org (Postfix) id E3EABB84E5; Sat, 6 Mar 2010 07:43:46 +1100 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: from e8.ny.us.ibm.com (e8.ny.us.ibm.com [32.97.182.138]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "e8.ny.us.ibm.com", Issuer "Equifax" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 65F57B815C for ; Sat, 6 Mar 2010 07:43:46 +1100 (EST) Received: from d01relay06.pok.ibm.com (d01relay06.pok.ibm.com [9.56.227.116]) by e8.ny.us.ibm.com (8.14.3/8.13.1) with ESMTP id o25KZlEO004414 for ; Fri, 5 Mar 2010 15:35:47 -0500 Received: from d01av01.pok.ibm.com (d01av01.pok.ibm.com [9.56.224.215]) by d01relay06.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id o25Khhen1806540 for ; Fri, 5 Mar 2010 15:43:43 -0500 Received: from d01av01.pok.ibm.com (loopback [127.0.0.1]) by d01av01.pok.ibm.com (8.14.3/8.13.1/NCO v10.0 AVout) with ESMTP id o25KhgUr008153 for ; Fri, 5 Mar 2010 15:43:43 -0500 Received: from norville.austin.ibm.com (norville.austin.ibm.com [9.41.46.96]) by d01av01.pok.ibm.com (8.14.3/8.13.1/NCO v10.0 AVin) with ESMTP id o25KhfoQ008113; Fri, 5 Mar 2010 15:43:41 -0500 Date: Fri, 5 Mar 2010 15:43:41 -0500 From: Dave Kleikamp To: linuxppc-dev list Message-Id: <20100305204341.18424.17797.sendpatchset@norville.austin.ibm.com> In-Reply-To: <20100305204255.18424.85295.sendpatchset@norville.austin.ibm.com> References: <20100305204255.18424.85295.sendpatchset@norville.austin.ibm.com> Subject: [PATCH 08/13] powerpc/476: define specific cpu table entry DD1.1 core Cc: Torez Smith X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org powerpc/476: define specific cpu table entry DD1.1 core From: Benjamin Herrenschmidt There are still some unstable bits in the DD1.1 cores. Don't use the FPU or the tlbivax operation. Define CPU_FTR_476_DD1_1 for additional workarounds in later patches. The DD1 core requires an additional workaround that will be addressed in a separate patch, which may not need to be picked up into the mainline kernel. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Dave Kleikamp --- arch/powerpc/include/asm/cputable.h | 1 + arch/powerpc/kernel/cputable.c | 26 ++++++++++++++++++++------ 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 9fff628..7c5d490 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -153,6 +153,7 @@ extern const char *powerpc_base_platform; #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000) #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000) #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000) +#define CPU_FTR_476_DD1_1 ASM_CONST(0x0000000000010000) #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index a06e6d3..cb9e6b7 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -1701,15 +1701,15 @@ static struct cpu_spec __initdata cpu_specs[] = { .machine_check = machine_check_440A, .platform = "ppc440", }, - { /* 476 core */ + { /* 476 DD1.1 core */ .pvr_mask = 0xffff0000, - .pvr_value = 0x11a50000, + .pvr_value = 0x11a52040, .cpu_name = "476", - .cpu_features = CPU_FTRS_47X, - .cpu_user_features = COMMON_USER_BOOKE | - PPC_FEATURE_HAS_FPU, + .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD1_1 | + CPU_FTR_FPU_UNAVAILABLE, + .cpu_user_features = COMMON_USER_BOOKE, .mmu_features = MMU_FTR_TYPE_47x | - MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, + MMU_FTR_LOCK_BCAST_INVAL, .icache_bsize = 32, .dcache_bsize = 128, .machine_check = machine_check_47x, @@ -1724,6 +1724,20 @@ static struct cpu_spec __initdata cpu_specs[] = { PPC_FEATURE_HAS_FPU, .cpu_user_features = COMMON_USER_BOOKE, .mmu_features = MMU_FTR_TYPE_47x | + MMU_FTR_LOCK_BCAST_INVAL, + .icache_bsize = 32, + .dcache_bsize = 128, + .machine_check = machine_check_47x, + .platform = "ppc470", + }, + { /* 476 others */ + .pvr_mask = 0xffff0000, + .pvr_value = 0x11a52000, + .cpu_name = "476", + .cpu_features = CPU_FTRS_47X, + .cpu_user_features = COMMON_USER_BOOKE | + PPC_FEATURE_HAS_FPU, + .mmu_features = MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, .icache_bsize = 32, .dcache_bsize = 128,