From patchwork Thu Mar 4 21:45:09 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 46983 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 148B2B7CF9 for ; Fri, 5 Mar 2010 08:52:22 +1100 (EST) Received: from localhost ([127.0.0.1]:49929 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NnIxY-000415-9u for incoming@patchwork.ozlabs.org; Thu, 04 Mar 2010 16:51:56 -0500 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NnIrl-0006Zk-Ld for qemu-devel@nongnu.org; Thu, 04 Mar 2010 16:45:57 -0500 Received: from [199.232.76.173] (port=42206 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NnIrk-0006Yy-TA for qemu-devel@nongnu.org; Thu, 04 Mar 2010 16:45:56 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1NnIrE-0005Ds-8d for qemu-devel@nongnu.org; Thu, 04 Mar 2010 16:45:56 -0500 Received: from hall.aurel32.net ([88.191.82.174]:33690) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NnIrD-0005DQ-Oi for qemu-devel@nongnu.org; Thu, 04 Mar 2010 16:45:24 -0500 Received: from [2a01:e35:2e80:2fb0:21e:8cff:feb0:693b] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1NnIrC-00019O-92; Thu, 04 Mar 2010 22:45:22 +0100 Received: from aurel32 by volta.aurel32.net with local (Exim 4.71) (envelope-from ) id 1NnIr5-0006yF-Jp; Thu, 04 Mar 2010 22:45:15 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Thu, 4 Mar 2010 22:45:09 +0100 Message-Id: <1267739110-26400-3-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.0 In-Reply-To: <1267739110-26400-1-git-send-email-aurelien@aurel32.net> References: <1267739110-26400-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: Andrzej Zaborowski , Aurelien Jarno Subject: [Qemu-devel] [PATCH 2/3] tcg/arm: use helpers for divu/remu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Aurelien Jarno --- tcg/arm/tcg-target.c | 94 -------------------------------------------------- tcg/arm/tcg-target.h | 1 - 2 files changed, 0 insertions(+), 95 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 756f131..0ff8f99 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -157,19 +157,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) # endif #endif - case '1': - ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); - break; - - case '2': - ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); - break; - default: return -1; } @@ -819,75 +806,6 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index) } } -static void tcg_out_div_helper(TCGContext *s, int cond, const TCGArg *args, - void *helper_div, void *helper_rem, int shift) -{ - int div_reg = args[0]; - int rem_reg = args[1]; - - /* stmdb sp!, { r0 - r3, ip, lr } */ - /* (Note that we need an even number of registers as per EABI) */ - tcg_out32(s, (cond << 28) | 0x092d500f); - - tcg_out_dat_reg(s, cond, ARITH_MOV, 0, 0, args[2], SHIFT_IMM_LSL(0)); - tcg_out_dat_reg(s, cond, ARITH_MOV, 1, 0, args[3], SHIFT_IMM_LSL(0)); - tcg_out_dat_reg(s, cond, ARITH_MOV, 2, 0, args[4], SHIFT_IMM_LSL(0)); - tcg_out_dat_reg(s, cond, ARITH_MOV, 3, 0, 2, shift); - - tcg_out_call(s, cond, (uint32_t) helper_div); - tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 0, SHIFT_IMM_LSL(0)); - - /* ldmia sp, { r0 - r3, fp, lr } */ - tcg_out32(s, (cond << 28) | 0x089d500f); - - tcg_out_dat_reg(s, cond, ARITH_MOV, 0, 0, args[2], SHIFT_IMM_LSL(0)); - tcg_out_dat_reg(s, cond, ARITH_MOV, 1, 0, args[3], SHIFT_IMM_LSL(0)); - tcg_out_dat_reg(s, cond, ARITH_MOV, 2, 0, args[4], SHIFT_IMM_LSL(0)); - tcg_out_dat_reg(s, cond, ARITH_MOV, 3, 0, 2, shift); - - tcg_out_call(s, cond, (uint32_t) helper_rem); - - tcg_out_dat_reg(s, cond, ARITH_MOV, rem_reg, 0, 0, SHIFT_IMM_LSL(0)); - tcg_out_dat_reg(s, cond, ARITH_MOV, div_reg, 0, 8, SHIFT_IMM_LSL(0)); - - /* ldr r0, [sp], #4 */ - if (rem_reg != 0 && div_reg != 0) { - tcg_out32(s, (cond << 28) | 0x04bd0004); - } else { - tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 4); - } - /* ldr r1, [sp], #4 */ - if (rem_reg != 1 && div_reg != 1) { - tcg_out32(s, (cond << 28) | 0x04bd1004); - } else { - tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 4); - } - /* ldr r2, [sp], #4 */ - if (rem_reg != 2 && div_reg != 2) { - tcg_out32(s, (cond << 28) | 0x04bd2004); - } else { - tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 4); - } - /* ldr r3, [sp], #4 */ - if (rem_reg != 3 && div_reg != 3) { - tcg_out32(s, (cond << 28) | 0x04bd3004); - } else { - tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 4); - } - /* ldr ip, [sp], #4 */ - if (rem_reg != 12 && div_reg != 12) { - tcg_out32(s, (cond << 28) | 0x04bdc004); - } else { - tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 4); - } - /* ldr lr, [sp], #4 */ - if (rem_reg != 14 && div_reg != 14) { - tcg_out32(s, (cond << 28) | 0x04bde004); - } else { - tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 4); - } -} - #ifdef CONFIG_SOFTMMU #include "../../softmmu_defs.h" @@ -1487,16 +1405,6 @@ static inline void tcg_out_op(TCGContext *s, int opc, case INDEX_op_mulu2_i32: tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); break; - case INDEX_op_div2_i32: - tcg_out_div_helper(s, COND_AL, args, - tcg_helper_div_i64, tcg_helper_rem_i64, - SHIFT_IMM_ASR(31)); - break; - case INDEX_op_divu2_i32: - tcg_out_div_helper(s, COND_AL, args, - tcg_helper_divu_i64, tcg_helper_remu_i64, - SHIFT_IMM_LSR(31)); - break; /* XXX: Perhaps args[2] & 0x1f is wrong */ case INDEX_op_shl_i32: c = const_args[2] ? @@ -1652,8 +1560,6 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_sub_i32, { "r", "r", "rI" } }, { INDEX_op_mul_i32, { "r", "r", "r" } }, { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } }, - { INDEX_op_div2_i32, { "r", "r", "r", "1", "2" } }, - { INDEX_op_divu2_i32, { "r", "r", "r", "1", "2" } }, { INDEX_op_and_i32, { "r", "r", "rI" } }, { INDEX_op_andc_i32, { "r", "r", "rI" } }, { INDEX_op_or_i32, { "r", "r", "rI" } }, diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 4b2b0be..4cad967 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -56,7 +56,6 @@ enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 /* optional instructions */ -#define TCG_TARGET_HAS_div2_i32 #define TCG_TARGET_HAS_ext8s_i32 #define TCG_TARGET_HAS_ext16s_i32 // #define TCG_TARGET_HAS_ext8u_i32