diff mbox

[1/3] soc/tegra: fuse: Add spare bit offset for Tegra114

Message ID 1430750923-23682-1-git-send-email-thierry.reding@gmail.com
State Superseded, archived
Headers show

Commit Message

Thierry Reding May 4, 2015, 2:48 p.m. UTC 
From: Thierry Reding <treding@nvidia.com>

The offset of the first spare bit register on Tegra114 is 0x280.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/soc/tegra/fuse/fuse-tegra30.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Thierry Reding May 4, 2015, 3:07 p.m. UTC | #1 
On Mon, May 04, 2015 at 04:48:41PM +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The offset of the first spare bit register on Tegra114 is 0x280.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  drivers/soc/tegra/fuse/fuse-tegra30.c | 1 +
>  1 file changed, 1 insertion(+)

I just realized that all these offsets are offset by 0x100 because they
use the generic fuse access operation. Will update the series to reflect
that.

Thierry
diff mbox

Patch

diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c
index 5a6c533417fc..a55664fda81e 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra30.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra30.c
@@ -117,6 +117,7 @@  const struct tegra_fuse_soc tegra30_fuse_soc = {
 static const struct tegra_fuse_info tegra114_fuse_info = {
 	.read = tegra30_fuse_read,
 	.size = 0x2a0,
+	.spare = 0x280,
 };
 
 const struct tegra_fuse_soc tegra114_fuse_soc = {