From patchwork Thu Apr 30 16:20:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 466623 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id BA09F14007F for ; Fri, 1 May 2015 02:21:38 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="verification failed; unprotected key" header.d=gmail.com header.i=@gmail.com header.b=L97Z3Mcu; dkim-adsp=none (unprotected policy); dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751747AbbD3QVW (ORCPT ); Thu, 30 Apr 2015 12:21:22 -0400 Received: from mail-wi0-f169.google.com ([209.85.212.169]:33928 "EHLO mail-wi0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751932AbbD3QVS (ORCPT ); Thu, 30 Apr 2015 12:21:18 -0400 Received: by wicmx19 with SMTP id mx19so16911448wic.1; Thu, 30 Apr 2015 09:21:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eU9Pbpy5UcNtF5zwqgl5kV/wA+B1v2uKLg9oq5t/psA=; b=L97Z3McuDL4U51cIDK/aOTI5/v1woy6QIfcq7VxJZiIFf3nS/MqZ6IcjElgU12lIz4 +m/8gnSVmclc6nyVsrmR7hF4jxyN7RSKFwKEx68XX6fg1TrxBUZ+NpKhJhnYCJ/8cFHv TH0swE1qezO1rHqf4zo7QaAP5ZecERAomEBQ79CAoZ54FDffrUost7Un2PnyCCBT244B wHL+pWACW7LHxPzS3ZAvyObycW9UAaWareZphj3RMKCKdqCG4446mO4wd+Jh8MAzX/47 eIeUvz+rNh++NnaoTZbIUa2vgqVAnlFmxZEIDHhovtF2IN+TEWb0sLCU0lACed7RJCp1 GMiw== X-Received: by 10.180.211.102 with SMTP id nb6mr6998907wic.32.1430410875840; Thu, 30 Apr 2015 09:21:15 -0700 (PDT) Received: from lmecul0520.st.com. (60.26.90.92.rev.sfr.net. [92.90.26.60]) by mx.google.com with ESMTPSA id ln8sm3971931wjc.18.2015.04.30.09.21.12 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Apr 2015 09:21:15 -0700 (PDT) From: Maxime Coquelin To: u.kleine-koenig@pengutronix.de, afaerber@suse.de, geert@linux-m68k.org, Rob Herring , Philipp Zabel , Linus Walleij , Arnd Bergmann , stefan@agner.ch, pmeerw@pmeerw.net, pebolle@tiscali.nl, peter@hurleysoftware.com, andy.shevchenko@gmail.com, cw00.choi@samsung.com, Russell King , Daniel Lezcano , joe@perches.com, Vladimir Zapolskiy Cc: Jonathan Corbet , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Andrew Morton , "David S. Miller" , Mauro Carvalho Chehab , Antti Palosaari , Tejun Heo , Will Deacon , Nikolay Borisov , Rusty Russell , Kees Cook , Michal Marek , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, mcoquelin.stm32@gmail.com, Nicolae Rosia , Kamil Lulko , Daniel Thompson Subject: [PATCH v7 07/15] dt-bindings: Document the STM32 timer bindings Date: Thu, 30 Apr 2015 18:20:36 +0200 Message-Id: <1430410844-16062-8-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430410844-16062-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1430410844-16062-1-git-send-email-mcoquelin.stm32@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds documentation of device tree bindings for the STM32 timer. Tested-by: Chanwoo Choi Acked-by: Rob Herring Signed-off-by: Maxime Coquelin --- .../devicetree/bindings/timer/st,stm32-timer.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/st,stm32-timer.txt diff --git a/Documentation/devicetree/bindings/timer/st,stm32-timer.txt b/Documentation/devicetree/bindings/timer/st,stm32-timer.txt new file mode 100644 index 0000000..8ef28e7 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/st,stm32-timer.txt @@ -0,0 +1,22 @@ +. STMicroelectronics STM32 timer + +The STM32 MCUs family has several general-purpose 16 and 32 bits timers. + +Required properties: +- compatible : Should be "st,stm32-timer" +- reg : Address and length of the register set +- clocks : Reference on the timer input clock +- interrupts : Reference to the timer interrupt + +Optional properties: +- resets: Reference to a reset controller asserting the timer + +Example: + +timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + resets = <&rrc 259>; + clocks = <&clk_pmtr1>; +};