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[v2,06/19] clk: tegra: pll-params: change misc_reg count from 3 -> 6

Message ID 1430328109-537-7-git-send-email-rklein@nvidia.com
State Superseded, archived
Headers show

Commit Message

Rhyland Klein April 29, 2015, 5:21 p.m. UTC 
From: Bill Huang <bilhuang@nvidia.com>

New SoC's may have more then 3 MISC registers, so bump up the
array size and use a #define to be more informative about the value.

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
---
 drivers/clk/tegra/clk.h |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
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Patch

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 4ea8b5b089cd..03babba1c3b4 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -156,6 +156,8 @@  struct div_nmp {
 	u8		override_divp_shift;
 };
 
+#define MAX_PLL_MISC_REG_COUNT	6
+
 /**
  * struct clk_pll_params - PLL parameters
  *
@@ -213,7 +215,7 @@  struct tegra_clk_pll_params {
 	u32		iddq_bit_idx;
 	u32		aux_reg;
 	u32		dyn_ramp_reg;
-	u32		ext_misc_reg[3];
+	u32		ext_misc_reg[MAX_PLL_MISC_REG_COUNT];
 	u32		pmc_divnm_reg;
 	u32		pmc_divp_reg;
 	u32		flags;