[v1,6/7] STM32F205: Connect the SPI device
diff mbox

Message ID b50fb92441823cea4dd211ef88ce8e51e0565dc0.1429949062.git.alistair@alistair23.me
State New
Headers show

Commit Message

Alistair Francis April 25, 2015, 8:19 a.m. UTC
Connect the SPI device to the STM32F205 SoC.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
---

 hw/arm/stm32f205_soc.c         | 22 ++++++++++++++++++++++
 include/hw/arm/stm32f205_soc.h |  3 +++
 2 files changed, 25 insertions(+)

Comments

Peter Crosthwaite April 25, 2015, 6:31 p.m. UTC | #1
"devices"

On Sat, Apr 25, 2015 at 1:19 AM, Alistair Francis <alistair23@gmail.com> wrote:
> Connect the SPI device to the STM32F205 SoC.
>

"devices".

Curious. Are you attaching the SPI slaves on the command line using -device?

Otherwise:

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

Regards,
Peter

> Signed-off-by: Alistair Francis <alistair@alistair23.me>
> ---
>
>  hw/arm/stm32f205_soc.c         | 22 ++++++++++++++++++++++
>  include/hw/arm/stm32f205_soc.h |  3 +++
>  2 files changed, 25 insertions(+)
>
> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
> index 641ecbb..cb8884f 100644
> --- a/hw/arm/stm32f205_soc.c
> +++ b/hw/arm/stm32f205_soc.c
> @@ -33,10 +33,13 @@ static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
>      0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
>  static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
>      0x40012200 };
> +static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
> +    0x40003C00 };
>
>  static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
>  static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
>  #define ADC_IRQ 18
> +static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};
>
>  static void stm32f205_soc_initfn(Object *obj)
>  {
> @@ -63,6 +66,12 @@ static void stm32f205_soc_initfn(Object *obj)
>                            TYPE_STM32F2XX_ADC);
>          qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default());
>      }
> +
> +    for (i = 0; i < STM_NUM_SPIS; i++) {
> +        object_initialize(&s->spi[i], sizeof(s->spi[i]),
> +                          TYPE_STM32F2XX_SPI);
> +        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
> +    }
>  }
>
>  static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
> @@ -150,6 +159,19 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
>          sysbus_mmio_map(busdev, 0, adc_addr[i]);
>          sysbus_connect_irq(busdev, 0, pic[ADC_IRQ]);
>      }
> +
> +    /* SPI 1 and 2 */
> +    for (i = 0; i < STM_NUM_SPIS; i++) {
> +        dev = DEVICE(&(s->spi[i]));
> +        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
> +        if (err != NULL) {
> +            error_propagate(errp, err);
> +            return;
> +        }
> +        busdev = SYS_BUS_DEVICE(dev);
> +        sysbus_mmio_map(busdev, 0, spi_addr[i]);
> +        sysbus_connect_irq(busdev, 0, pic[spi_irq[i]]);
> +    }
>  }
>
>  static Property stm32f205_soc_properties[] = {
> diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
> index 7d6603b..00c2f3d 100644
> --- a/include/hw/arm/stm32f205_soc.h
> +++ b/include/hw/arm/stm32f205_soc.h
> @@ -29,6 +29,7 @@
>  #include "hw/timer/stm32f2xx_timer.h"
>  #include "hw/char/stm32f2xx_usart.h"
>  #include "hw/misc/stm32f2xx_adc.h"
> +#include "hw/ssi/stm32f2xx_spi.h"
>
>  #define TYPE_STM32F205_SOC "stm32f205-soc"
>  #define STM32F205_SOC(obj) \
> @@ -37,6 +38,7 @@
>  #define STM_NUM_USARTS 6
>  #define STM_NUM_TIMERS 4
>  #define STM_NUM_ADCS 3
> +#define STM_NUM_SPIS 3
>
>  #define FLASH_BASE_ADDRESS 0x08000000
>  #define FLASH_SIZE (1024 * 1024)
> @@ -55,6 +57,7 @@ typedef struct STM32F205State {
>      STM32F2XXUsartState usart[STM_NUM_USARTS];
>      STM32F2XXTimerState timer[STM_NUM_TIMERS];
>      STM32F2XXAdcState adc[STM_NUM_ADCS];
> +    STM32F2XXSpiState spi[STM_NUM_SPIS];
>  } STM32F205State;
>
>  #endif
> --
> 2.1.4
>
>

Patch
diff mbox

diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index 641ecbb..cb8884f 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -33,10 +33,13 @@  static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
     0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
 static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
     0x40012200 };
+static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
+    0x40003C00 };
 
 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
 #define ADC_IRQ 18
+static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};
 
 static void stm32f205_soc_initfn(Object *obj)
 {
@@ -63,6 +66,12 @@  static void stm32f205_soc_initfn(Object *obj)
                           TYPE_STM32F2XX_ADC);
         qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default());
     }
+
+    for (i = 0; i < STM_NUM_SPIS; i++) {
+        object_initialize(&s->spi[i], sizeof(s->spi[i]),
+                          TYPE_STM32F2XX_SPI);
+        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
+    }
 }
 
 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -150,6 +159,19 @@  static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
         sysbus_mmio_map(busdev, 0, adc_addr[i]);
         sysbus_connect_irq(busdev, 0, pic[ADC_IRQ]);
     }
+
+    /* SPI 1 and 2 */
+    for (i = 0; i < STM_NUM_SPIS; i++) {
+        dev = DEVICE(&(s->spi[i]));
+        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
+        if (err != NULL) {
+            error_propagate(errp, err);
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, spi_addr[i]);
+        sysbus_connect_irq(busdev, 0, pic[spi_irq[i]]);
+    }
 }
 
 static Property stm32f205_soc_properties[] = {
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
index 7d6603b..00c2f3d 100644
--- a/include/hw/arm/stm32f205_soc.h
+++ b/include/hw/arm/stm32f205_soc.h
@@ -29,6 +29,7 @@ 
 #include "hw/timer/stm32f2xx_timer.h"
 #include "hw/char/stm32f2xx_usart.h"
 #include "hw/misc/stm32f2xx_adc.h"
+#include "hw/ssi/stm32f2xx_spi.h"
 
 #define TYPE_STM32F205_SOC "stm32f205-soc"
 #define STM32F205_SOC(obj) \
@@ -37,6 +38,7 @@ 
 #define STM_NUM_USARTS 6
 #define STM_NUM_TIMERS 4
 #define STM_NUM_ADCS 3
+#define STM_NUM_SPIS 3
 
 #define FLASH_BASE_ADDRESS 0x08000000
 #define FLASH_SIZE (1024 * 1024)
@@ -55,6 +57,7 @@  typedef struct STM32F205State {
     STM32F2XXUsartState usart[STM_NUM_USARTS];
     STM32F2XXTimerState timer[STM_NUM_TIMERS];
     STM32F2XXAdcState adc[STM_NUM_ADCS];
+    STM32F2XXSpiState spi[STM_NUM_SPIS];
 } STM32F205State;
 
 #endif