From patchwork Sat Apr 25 08:18:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 464465 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id DE3DD14011B for ; Sat, 25 Apr 2015 18:19:24 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="verification failed; unprotected key" header.d=gmail.com header.i=@gmail.com header.b=Vy1V58Qs; dkim-adsp=none (unprotected policy); dkim-atps=neutral Received: from localhost ([::1]:47611 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YlvJ5-0002qP-15 for incoming@patchwork.ozlabs.org; Sat, 25 Apr 2015 04:19:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58584) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YlvIU-0001kf-1I for qemu-devel@nongnu.org; Sat, 25 Apr 2015 04:18:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YlvIQ-0000Lg-Rt for qemu-devel@nongnu.org; Sat, 25 Apr 2015 04:18:45 -0400 Received: from mail-pa0-x22c.google.com ([2607:f8b0:400e:c03::22c]:33391) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YlvIQ-0000Kv-Kz for qemu-devel@nongnu.org; Sat, 25 Apr 2015 04:18:42 -0400 Received: by pacwv17 with SMTP id wv17so49260069pac.0 for ; Sat, 25 Apr 2015 01:18:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2rBYHKhM6Te9TPO3GURsQgc0ZZgD7yEPYapisTKHC9E=; b=Vy1V58QsCfm/MhJXas3fdD+F7duuPSHC0u7smK2bHvhbyjYPWcyK2KU0jwPvBA7qzi hoJTcZN8fyF+IuboZO43IqWvlW4Xali8UosUFcN9TGbQZ3QNphhs005Mgpb9JLZABynV zIupYYkZxRMFasDlAtec8RmQBJPol4mk9ZBeETgBNbgVP1f4XcMkowHDOsAe8Mo/3q/y hyYy42FhLTkO4PRRLPfsp7W+5iyW0OxEK/zYRWYaocq7rlb1Pkdcg6Qslj3wnq6uxGa9 VjrS+XG9hS9BdPt8Jf2LsH4ERJ1wMjFTL6pCxgH029LX6/XkVcg++hlrGdaJj6COLg5B YWyg== X-Received: by 10.70.41.135 with SMTP id f7mr4256996pdl.113.1429949922079; Sat, 25 Apr 2015 01:18:42 -0700 (PDT) Received: from localhost (220-245-42-228.tpgi.com.au. [220.245.42.228]) by mx.google.com with ESMTPSA id y4sm13274477pdm.9.2015.04.25.01.18.40 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 25 Apr 2015 01:18:41 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sat, 25 Apr 2015 18:18:38 +1000 Message-Id: <0518e12fcfdc56dec44319dd28330bd9c871a2a5.1429949062.git.alistair@alistair23.me> X-Mailer: git-send-email 2.1.4 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::22c Cc: alistair23@gmail.com Subject: [Qemu-devel] [PATCH v1 2/7] STM32F2xx: Display PWM duty cycle from timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org If correctly configured allow the STM32F2xx timer to print out the PWM duty cycle information. Signed-off-by: Alistair Francis --- hw/timer/stm32f2xx_timer.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c index ecadf9d..6f463e8 100644 --- a/hw/timer/stm32f2xx_timer.c +++ b/hw/timer/stm32f2xx_timer.c @@ -49,6 +49,16 @@ static void stm32f2xx_timer_interrupt(void *opaque) qemu_irq_pulse(s->irq); stm32f2xx_timer_set_alarm(s, s->hit_time); } + + if (s->tim_ccmr1 & (TIM_CCMR1_OC2M2 + TIM_CCMR1_OC2M1) && + !(s->tim_ccmr1 & TIM_CCMR1_OC2M0) && + (s->tim_ccmr1 & TIM_CCMR1_OC2PE) && + s->tim_ccer & TIM_CCER_CC2E) { + /* PWM 2 - Mode 1 */ + DB_PRINT("Duty Cycle: %d%%\n", + s->tim_ccr2 / (100 * (s->tim_psc + 1))); + stm32f2xx_timer_set_alarm(s, s->hit_time); + } } static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t)