| Message ID | 1429798535-660-5-git-send-email-jagannadh.teki@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
Hi Jagan, On 23 April 2015 at 08:15, Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> wrote: > Now zynq spi driver platform data is controlled by devicetree, > enable the status by saying "okay" on respective board dts to use > the devicetree generated platdata. > > Ex: > &spi1 { > status = "okay"; > }; > > Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> > Cc: Simon Glass <sjg@chromium.org> > Cc: Michal Simek <michal.simek@xilinx.com> > Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> > --- > arch/arm/dts/zynq-7000.dtsi | 2 ++ > arch/arm/include/asm/arch-zynq/hardware.h | 2 -- > doc/device-tree-bindings/spi/spi-zynq.txt | 2 ++ > drivers/spi/zynq_spi.c | 23 +++++++++++++---------- > 4 files changed, 17 insertions(+), 12 deletions(-) Acked-by: Simon Glass <sjg@chromium.org> > > diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi > index f66f8dc..9207159 100644 > --- a/arch/arm/dts/zynq-7000.dtsi > +++ b/arch/arm/dts/zynq-7000.dtsi > @@ -117,6 +117,7 @@ > interrupts = <0 26 4>; > clocks = <&clkc 25>, <&clkc 34>; > clock-names = "ref_clk", "pclk"; > + spi-max-frequency = <166666700>; > #address-cells = <1>; > #size-cells = <0>; > }; > @@ -129,6 +130,7 @@ > interrupts = <0 49 4>; > clocks = <&clkc 26>, <&clkc 35>; > clock-names = "ref_clk", "pclk"; > + spi-max-frequency = <166666700>; > #address-cells = <1>; > #size-cells = <0>; > }; > diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h > index e2e0b73..df9b06b 100644 > --- a/arch/arm/include/asm/arch-zynq/hardware.h > +++ b/arch/arm/include/asm/arch-zynq/hardware.h > @@ -19,8 +19,6 @@ > #define ZYNQ_SDHCI_BASEADDR1 0xE0101000 > #define ZYNQ_I2C_BASEADDR0 0xE0004000 > #define ZYNQ_I2C_BASEADDR1 0xE0005000 > -#define ZYNQ_SPI_BASEADDR0 0xE0006000 > -#define ZYNQ_SPI_BASEADDR1 0xE0007000 > #define ZYNQ_QSPI_BASEADDR 0xE000D000 > #define ZYNQ_SMC_BASEADDR 0xE000E000 > #define ZYNQ_NAND_BASEADDR 0xE1000000 > diff --git a/doc/device-tree-bindings/spi/spi-zynq.txt b/doc/device-tree-bindings/spi/spi-zynq.txt > index a7c2757..f397a36 100644 > --- a/doc/device-tree-bindings/spi/spi-zynq.txt > +++ b/doc/device-tree-bindings/spi/spi-zynq.txt > @@ -11,6 +11,7 @@ Required properties: > - clocks : Clock phandles (see clock bindings for details). > - clock-names : List of input clock names - "ref_clk", "pclk" > (See clock bindings for details). > +- spi-max-frequency : Maximum SPI clocking speed of device in Hz > > Example: > > @@ -22,6 +23,7 @@ Example: > interrupts = <0 26 4>; > clocks = <&clkc 25>, <&clkc 34>; > clock-names = "ref_clk", "pclk"; > + spi-max-frequency = <166666700>; > #address-cells = <1>; > #size-cells = <0>; > } ; > diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c > index 62edbbe..df4a99e 100644 > --- a/drivers/spi/zynq_spi.c > +++ b/drivers/spi/zynq_spi.c > @@ -13,9 +13,12 @@ > #include <errno.h> > #include <malloc.h> > #include <spi.h> > +#include <fdtdec.h> > #include <asm/io.h> > #include <asm/arch/hardware.h> > > +DECLARE_GLOBAL_DATA_PTR; > + > /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */ > #define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */ > #define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */ > @@ -64,22 +67,22 @@ struct zynq_spi_priv { > u32 freq; /* required frequency */ > }; > > -static inline struct zynq_spi_regs *get_zynq_spi_regs(struct udevice *bus) > -{ > - if (bus->seq) > - return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1; > - else > - return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0; > -} > - > static int zynq_spi_ofdata_to_platdata(struct udevice *bus) > { > struct zynq_spi_platdata *plat = bus->platdata; > + const void *blob = gd->fdt_blob; > + int node = bus->of_offset; > + > + plat->regs = (struct zynq_spi_regs *)fdtdec_get_addr(blob, node, "reg"); Or dev_get_addr() if you like. > > - plat->regs = get_zynq_spi_regs(bus); > - plat->frequency = 166666700; > + /* FIXME: Use 250MHz as a suitable default */ > + plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", > + 250000000); > plat->speed_hz = plat->frequency / 2; > > + debug("zynq_spi_ofdata_to_platdata: regs=%p max-frequency=%d\n", > + plat->regs, plat->frequency); > + > return 0; > } > > -- > 1.9.1 > Regards, Simon
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index f66f8dc..9207159 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -117,6 +117,7 @@ interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; + spi-max-frequency = <166666700>; #address-cells = <1>; #size-cells = <0>; }; @@ -129,6 +130,7 @@ interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; + spi-max-frequency = <166666700>; #address-cells = <1>; #size-cells = <0>; }; diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index e2e0b73..df9b06b 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -19,8 +19,6 @@ #define ZYNQ_SDHCI_BASEADDR1 0xE0101000 #define ZYNQ_I2C_BASEADDR0 0xE0004000 #define ZYNQ_I2C_BASEADDR1 0xE0005000 -#define ZYNQ_SPI_BASEADDR0 0xE0006000 -#define ZYNQ_SPI_BASEADDR1 0xE0007000 #define ZYNQ_QSPI_BASEADDR 0xE000D000 #define ZYNQ_SMC_BASEADDR 0xE000E000 #define ZYNQ_NAND_BASEADDR 0xE1000000 diff --git a/doc/device-tree-bindings/spi/spi-zynq.txt b/doc/device-tree-bindings/spi/spi-zynq.txt index a7c2757..f397a36 100644 --- a/doc/device-tree-bindings/spi/spi-zynq.txt +++ b/doc/device-tree-bindings/spi/spi-zynq.txt @@ -11,6 +11,7 @@ Required properties: - clocks : Clock phandles (see clock bindings for details). - clock-names : List of input clock names - "ref_clk", "pclk" (See clock bindings for details). +- spi-max-frequency : Maximum SPI clocking speed of device in Hz Example: @@ -22,6 +23,7 @@ Example: interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; + spi-max-frequency = <166666700>; #address-cells = <1>; #size-cells = <0>; } ; diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 62edbbe..df4a99e 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -13,9 +13,12 @@ #include <errno.h> #include <malloc.h> #include <spi.h> +#include <fdtdec.h> #include <asm/io.h> #include <asm/arch/hardware.h> +DECLARE_GLOBAL_DATA_PTR; + /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */ #define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */ #define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */ @@ -64,22 +67,22 @@ struct zynq_spi_priv { u32 freq; /* required frequency */ }; -static inline struct zynq_spi_regs *get_zynq_spi_regs(struct udevice *bus) -{ - if (bus->seq) - return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1; - else - return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0; -} - static int zynq_spi_ofdata_to_platdata(struct udevice *bus) { struct zynq_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + + plat->regs = (struct zynq_spi_regs *)fdtdec_get_addr(blob, node, "reg"); - plat->regs = get_zynq_spi_regs(bus); - plat->frequency = 166666700; + /* FIXME: Use 250MHz as a suitable default */ + plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", + 250000000); plat->speed_hz = plat->frequency / 2; + debug("zynq_spi_ofdata_to_platdata: regs=%p max-frequency=%d\n", + plat->regs, plat->frequency); + return 0; }
Now zynq spi driver platform data is controlled by devicetree, enable the status by saying "okay" on respective board dts to use the devicetree generated platdata. Ex: &spi1 { status = "okay"; }; Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> --- arch/arm/dts/zynq-7000.dtsi | 2 ++ arch/arm/include/asm/arch-zynq/hardware.h | 2 -- doc/device-tree-bindings/spi/spi-zynq.txt | 2 ++ drivers/spi/zynq_spi.c | 23 +++++++++++++---------- 4 files changed, 17 insertions(+), 12 deletions(-)