diff mbox

target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled

Message ID 1429669112-29835-1-git-send-email-serge.fdrv@gmail.com
State New
Headers show

Commit Message

Sergey Fedorov April 22, 2015, 2:18 a.m. UTC
Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
---
 target-arm/cpu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Greg Bellows April 22, 2015, 2:04 p.m. UTC | #1
On Tue, Apr 21, 2015 at 9:18 PM, Sergey Fedorov <serge.fdrv@gmail.com>
wrote:

> Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
> ---
>  target-arm/cpu.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 986f04c..327b1e5 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -524,9 +524,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
> **errp)
>          unset_feature(env, ARM_FEATURE_EL3);
>
>          /* Disable the security extension feature bits in the processor
> feature
> -         * register as well.  This is id_pfr1[7:4].
> +         * registers as well. These are id_pfr1[7:4] and
> id_aa64pfr0[15:12].
>           */
>          cpu->id_pfr1 &= ~0xf0;
> +        cpu->id_aa64pfr0 &= ~0xf000;
>      }
>
>      register_cp_regs_for_features(cpu);
> --
> 2.3.4
>
>
> ​​Reviewed-by: Greg Bellows <greg.bellows@linaro.org>​​
Peter Maydell April 23, 2015, 12:25 p.m. UTC | #2
On 22 April 2015 at 03:18, Sergey Fedorov <serge.fdrv@gmail.com> wrote:
> Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
> ---
>  target-arm/cpu.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)



Applied to target-arm.next, thanks.

-- PMM
diff mbox

Patch

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 986f04c..327b1e5 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -524,9 +524,10 @@  static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         unset_feature(env, ARM_FEATURE_EL3);
 
         /* Disable the security extension feature bits in the processor feature
-         * register as well.  This is id_pfr1[7:4].
+         * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
          */
         cpu->id_pfr1 &= ~0xf0;
+        cpu->id_aa64pfr0 &= ~0xf000;
     }
 
     register_cp_regs_for_features(cpu);