| Message ID | 227f8c75e04110e279b78512924742ba7c7fe5fc.1429586144.git.dhdang@apm.com |
|---|---|
| State | Superseded |
| Headers | show |
On 21/04/15 05:04, Duc Dang wrote: > There is single MSI block in X-Gene v1 SOC which serves all 5 PCIe ports. > > Signed-off-by: Duc Dang <dhdang@apm.com> > Signed-off-by: Tanmay Inamdar <tinamdar@apm.com> > --- > arch/arm64/boot/dts/apm/apm-storm.dtsi | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi > index f1ad9c2..4b719c9 100644 > --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi > +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi > @@ -354,6 +354,28 @@ > }; > }; > > + msi: msi@79000000 { > + compatible = "apm,xgene1-msi"; > + msi-controller; > + reg = <0x00 0x79000000 0x0 0x900000>; I've been repeatedly puzzled by the size of this region. In patch 1, you say: + * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where + * n is group number (0..F), x is index of registers in each group (0..7) + * The registers layout is like following: + * MSI0IR0 base_addr + * MSI0IR1 base_addr + 0x10000 + * ... ... + * MSI0IR6 base_addr + 0x60000 + * MSI0IR7 base_addr + 0x70000 + * MSI1IR0 base_addr + 0x80000 + * MSI1IR1 base_addr + 0x90000 + * ... ... + * MSI1IR7 base_addr + 0xF0000 + * MSI2IR0 base_addr + 0x100000 + * ... ... + * MSIFIR0 base_addr + 0x780000 + * MSIFIR1 base_addr + 0x790000 + * ... ... + * MSIFIR7 base_addr + 0x7F0000 which implies that the size of the region is 0x800000. Or is there something hidden in the last 16 64k pages? Thanks, M.
On Tue, Apr 21, 2015 at 8:19 AM, Marc Zyngier <marc.zyngier@arm.com> wrote: > On 21/04/15 05:04, Duc Dang wrote: >> There is single MSI block in X-Gene v1 SOC which serves all 5 PCIe ports. >> >> Signed-off-by: Duc Dang <dhdang@apm.com> >> Signed-off-by: Tanmay Inamdar <tinamdar@apm.com> >> --- >> arch/arm64/boot/dts/apm/apm-storm.dtsi | 27 +++++++++++++++++++++++++++ >> 1 file changed, 27 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi >> index f1ad9c2..4b719c9 100644 >> --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi >> +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi >> @@ -354,6 +354,28 @@ >> }; >> }; >> >> + msi: msi@79000000 { >> + compatible = "apm,xgene1-msi"; >> + msi-controller; >> + reg = <0x00 0x79000000 0x0 0x900000>; > > I've been repeatedly puzzled by the size of this region. In patch 1, you > say: > > + * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where > + * n is group number (0..F), x is index of registers in each group (0..7) > + * The registers layout is like following: > + * MSI0IR0 base_addr > + * MSI0IR1 base_addr + 0x10000 > + * ... ... > + * MSI0IR6 base_addr + 0x60000 > + * MSI0IR7 base_addr + 0x70000 > + * MSI1IR0 base_addr + 0x80000 > + * MSI1IR1 base_addr + 0x90000 > + * ... ... > + * MSI1IR7 base_addr + 0xF0000 > + * MSI2IR0 base_addr + 0x100000 > + * ... ... > + * MSIFIR0 base_addr + 0x780000 > + * MSIFIR1 base_addr + 0x790000 > + * ... ... > + * MSIFIR7 base_addr + 0x7F0000 > > which implies that the size of the region is 0x800000. Or is there > something hidden in the last 16 64k pages? The registers listed in the first patch are termination registers. From offset 0x800000 to 0x8f0000, the MSI controller provides status registers for software to check if there is pending MSI interrupt in each MSI group (in the code we read MSI_INTx registers starting from 0x800000 to check if there is an MSI interrupt pending). > > Thanks, > > M. > -- > Jazz is not dead. It just smells funny... Regards, Duc Dang. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index f1ad9c2..4b719c9 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -354,6 +354,28 @@ }; }; + msi: msi@79000000 { + compatible = "apm,xgene1-msi"; + msi-controller; + reg = <0x00 0x79000000 0x0 0x900000>; + interrupts = < 0x0 0x10 0x4 + 0x0 0x11 0x4 + 0x0 0x12 0x4 + 0x0 0x13 0x4 + 0x0 0x14 0x4 + 0x0 0x15 0x4 + 0x0 0x16 0x4 + 0x0 0x17 0x4 + 0x0 0x18 0x4 + 0x0 0x19 0x4 + 0x0 0x1a 0x4 + 0x0 0x1b 0x4 + 0x0 0x1c 0x4 + 0x0 0x1d 0x4 + 0x0 0x1e 0x4 + 0x0 0x1f 0x4>; + }; + pcie0: pcie@1f2b0000 { status = "disabled"; device_type = "pci"; @@ -375,6 +397,7 @@ 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; dma-coherent; clocks = <&pcie0clk 0>; + msi-parent = <&msi>; }; pcie1: pcie@1f2c0000 { @@ -398,6 +421,7 @@ 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>; dma-coherent; clocks = <&pcie1clk 0>; + msi-parent = <&msi>; }; pcie2: pcie@1f2d0000 { @@ -421,6 +445,7 @@ 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>; dma-coherent; clocks = <&pcie2clk 0>; + msi-parent = <&msi>; }; pcie3: pcie@1f500000 { @@ -444,6 +469,7 @@ 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>; dma-coherent; clocks = <&pcie3clk 0>; + msi-parent = <&msi>; }; pcie4: pcie@1f510000 { @@ -467,6 +493,7 @@ 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>; dma-coherent; clocks = <&pcie4clk 0>; + msi-parent = <&msi>; }; serial0: serial@1c020000 {