From patchwork Tue Feb 23 20:21:31 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: target-ppc: fix SPE evsplat* instructions Date: Tue, 23 Feb 2010 10:21:31 -0000 From: Nathan Froyd X-Patchwork-Id: 46097 Message-Id: <1266956491-30704-1-git-send-email-froydnj@codesourcery.com> To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net The shifts in the gen_evsplat* functions were expecting rA to be masked, not extracted, and so used the wrong shift amounts to sign-extend or pad with zeroes. Signed-off-by: Nathan Froyd --- target-ppc/translate.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index d4e81ce..0b11fda 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7001,7 +7001,7 @@ static inline void gen_evmergelohi(DisasContext *ctx) } static inline void gen_evsplati(DisasContext *ctx) { - uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27; + uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; #if defined(TARGET_PPC64) tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); @@ -7012,7 +7012,7 @@ static inline void gen_evsplati(DisasContext *ctx) } static inline void gen_evsplatfi(DisasContext *ctx) { - uint64_t imm = rA(ctx->opcode) << 11; + uint64_t imm = rA(ctx->opcode) << 27; #if defined(TARGET_PPC64) tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);