diff mbox

ixgbe: Release semaphore bits in the right order

Message ID 20150410173631.9380.46865.stgit@mdrustad-wks.jf.intel.com
State Accepted
Delegated to: Jeff Kirsher
Headers show

Commit Message

Rustad, Mark D April 10, 2015, 5:36 p.m. UTC
The global semaphore bits should be released in the reverse of the
order that they were taken, so correct that.

Signed-off-by: Mark Rustad <mark.d.rustad@intel.com>
---
 0 files changed

Comments

Kirsher, Jeffrey T April 10, 2015, 10:55 p.m. UTC | #1
On Fri, 2015-04-10 at 10:36 -0700, Mark D Rustad wrote:
> The global semaphore bits should be released in the reverse of the
> order that they were taken, so correct that.
> 
> Signed-off-by: Mark Rustad <mark.d.rustad@intel.com>

Thanks Mark, I have applied your patch to my queue.
Phil Schmitt April 22, 2015, 10:43 p.m. UTC | #2
> -----Original Message-----
> From: Intel-wired-lan [mailto:intel-wired-lan-bounces@lists.osuosl.org] On
> Behalf Of Jeff Kirsher
> Sent: Friday, April 10, 2015 3:56 PM
> To: Rustad, Mark D
> Cc: intel-wired-lan@lists.osuosl.org
> Subject: Re: [Intel-wired-lan] [PATCH] ixgbe: Release semaphore bits in the right
> order
> 
> On Fri, 2015-04-10 at 10:36 -0700, Mark D Rustad wrote:
> > The global semaphore bits should be released in the reverse of the
> > order that they were taken, so correct that.
> >
> > Signed-off-by: Mark Rustad <mark.d.rustad@intel.com>
> 
> Thanks Mark, I have applied your patch to my queue.
> --
> git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue.git
> dev-queue

Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
diff mbox

Patch

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
index f5f948d08b43..0a8b5e42e1a9 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
@@ -696,14 +696,14 @@  static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
 
 	/* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
 
-	swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
-	swsm &= ~IXGBE_SWSM_SMBI;
-	IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
-
 	swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 	swsm &= ~IXGBE_SWFW_REGSMP;
 	IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
 
+	swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+	swsm &= ~IXGBE_SWSM_SMBI;
+	IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
+
 	IXGBE_WRITE_FLUSH(hw);
 }