From patchwork Tue Apr 7 16:30:21 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 458710 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D3D8C1402BB for ; Wed, 8 Apr 2015 02:31:37 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="verification failed; unprotected key" header.d=gmail.com header.i=@gmail.com header.b=IoxecOoJ; dkim-adsp=none (unprotected policy); dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753173AbbDGQbc (ORCPT ); Tue, 7 Apr 2015 12:31:32 -0400 Received: from mail-wg0-f45.google.com ([74.125.82.45]:36111 "EHLO mail-wg0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753128AbbDGQbX (ORCPT ); Tue, 7 Apr 2015 12:31:23 -0400 Received: by wgsk9 with SMTP id k9so39315601wgs.3; Tue, 07 Apr 2015 09:31:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=7+t5k/jpltEHEkELUxNCPvwn5TheuJyBZV9DqxzNUGk=; b=IoxecOoJy1yH2c/QZfgWFgqe6AC/y2kJcqdX/rG7YPeGPUbmQuMQBhky+rN+iv63ci xOWCRDfrHYvF5rR6rCKUFUlrCh0VXPQ8USGDDxiDYXGtXHM1PN4zEiXVpOo/W8C/tSHv yg9QrBv0XRPY0VWa1VWcj0mJg6UUeQTniDs4ZOeqHvS8KenEpg8YOFeUXUKn2j5ud8pu 5w2zzdjq2SMZ4dNvKHPIHaY4nONwbys3HxlONF2rN4W6BPfjzt+v1IKZh6xqZF3kQJpM b1eRbPQa6DM1AuHhtqF6p+UmN+63BholZINwjwDJ4fwhpOhXPvbu2qYu5sAhY+q35PFi VHfw== X-Received: by 10.180.14.67 with SMTP id n3mr5995257wic.92.1428424281015; Tue, 07 Apr 2015 09:31:21 -0700 (PDT) Received: from lmecul0520.st.com. (58.26.90.92.rev.sfr.net. [92.90.26.58]) by mx.google.com with ESMTPSA id gt4sm11681251wib.21.2015.04.07.09.31.18 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 07 Apr 2015 09:31:20 -0700 (PDT) From: Maxime Coquelin To: u.kleine-koenig@pengutronix.de, afaerber@suse.de, geert@linux-m68k.org, Rob Herring , Philipp Zabel , Linus Walleij , Arnd Bergmann , stefan@agner.ch, pmeerw@pmeerw.net, pebolle@tiscali.nl, peter@hurleysoftware.com, andy.shevchenko@gmail.com, cw00.choi@samsung.com, Russell King , Daniel Lezcano , joe@perches.com Cc: Jonathan Corbet , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Andrew Morton , "David S. Miller" , Mauro Carvalho Chehab , Antti Palosaari , Tejun Heo , Will Deacon , Nikolay Borisov , Rusty Russell , Kees Cook , Michal Marek , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, mcoquelin.stm32@gmail.com Subject: [PATCH v6 02/15] ARM: ARMv7-M: Enlarge vector table up to 256 entries Date: Tue, 7 Apr 2015 18:30:21 +0200 Message-Id: <1428424234-28572-3-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1428424234-28572-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1428424234-28572-1-git-send-email-mcoquelin.stm32@gmail.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From Cortex-M reference manuals, the nvic supports up to 240 interrupts. So the number of entries in vectors table is up to 256. This patch adds a new config flag to specify the number of external interrupts. Some ifdeferies are added in order to respect the natural alignment without wasting too much space on smaller systems. Acked-by: Uwe Kleine-König Acked-by: Stefan Agner Tested-by: Chanwoo Choi Signed-off-by: Maxime Coquelin --- arch/arm/kernel/entry-v7m.S | 13 +++++++++---- arch/arm/mm/Kconfig | 15 +++++++++++++++ 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S index 8944f49..b6c8bb9 100644 --- a/arch/arm/kernel/entry-v7m.S +++ b/arch/arm/kernel/entry-v7m.S @@ -117,9 +117,14 @@ ENTRY(__switch_to) ENDPROC(__switch_to) .data - .align 8 +#if CONFIG_CPU_V7M_NUM_IRQ <= 112 + .align 9 +#else + .align 10 +#endif + /* - * Vector table (64 words => 256 bytes natural alignment) + * Vector table (Natural alignment need to be ensured) */ ENTRY(vector_table) .long 0 @ 0 - Reset stack pointer @@ -138,6 +143,6 @@ ENTRY(vector_table) .long __invalid_entry @ 13 - Reserved .long __pendsv_entry @ 14 - PendSV .long __invalid_entry @ 15 - SysTick - .rept 64 - 16 - .long __irq_entry @ 16..64 - External Interrupts + .rept CONFIG_CPU_V7M_NUM_IRQ + .long __irq_entry @ External Interrupts .endr diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 9b4f29e..aec53b4 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -604,6 +604,21 @@ config CPU_USE_DOMAINS This option enables or disables the use of domain switching via the set_fs() function. +config CPU_V7M_NUM_IRQ + int "Number of external interrupts connected to the NVIC" + depends on CPU_V7M + default 90 if ARCH_STM32 + default 38 if ARCH_EFM32 + default 240 + help + This option indicates the number of interrupts connected to the NVIC. + The value can be larger than the real number of interrupts supported + by the system, but must not be lower. + The default value is 240, corresponding to the maximum number of + interrupts supported by the NVIC on Cortex-M family. + + If unsure, keep default value. + # # CPU supports 36-bit I/O #