| Message ID | 1428346870-15227-1-git-send-email-nitin.garg@freescale.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Stefano Babic |
| Headers | show |
On 4/6/2015 12:01 PM, nitin.garg@freescale.com wrote: > From: Nitin Garg <nitin.garg@freescale.com> > > Since MX6 is Cortex-A9 r2p10, enable ARM errata > 751472, 794072, 761320 only applied to the > following configuration: > > This erratum affects configurations with either: > - One processor if the ACP is present > - Two or more processors > > i.MX6 family does not have the ACP and thus only the MPCore > system will be impacted, which are the i.MX6DQ, i.MX6DL. > > Signed-off-by: Nitin Garg <nitin.garg@freescale.com> > --- > > Changes in v3: > Split the patch as suggested by Fabio. > > Changes in v2: None > > include/configs/mx6_common.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h > index e0528ce..e22336e 100644 > --- a/include/configs/mx6_common.h > +++ b/include/configs/mx6_common.h > @@ -18,9 +18,12 @@ > #define __MX6_COMMON_H > > #define CONFIG_ARM_ERRATA_743622 > +#if (defined(CONFIG_MX6Q) || defined(CONFIG_MX6DL) ||\ > +defined(CONFIG_MX6QDL)) && !defined(CONFIG_MX6S) > #define CONFIG_ARM_ERRATA_751472 > #define CONFIG_ARM_ERRATA_794072 > #define CONFIG_ARM_ERRATA_761320 > +#endif We definitely want to allow 1 binary for CONFIG_MX6DL/ CONFIG_MX6S so perhaps this needs to be a runtime check ? Thanks Troy
Hi Troy, Nitin, On 07/04/2015 01:33, Troy Kisky wrote: > On 4/6/2015 12:01 PM, nitin.garg@freescale.com wrote: >> From: Nitin Garg <nitin.garg@freescale.com> >> >> Since MX6 is Cortex-A9 r2p10, enable ARM errata >> 751472, 794072, 761320 only applied to the >> following configuration: >> >> This erratum affects configurations with either: >> - One processor if the ACP is present >> - Two or more processors >> >> i.MX6 family does not have the ACP and thus only the MPCore >> system will be impacted, which are the i.MX6DQ, i.MX6DL. >> >> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> >> --- >> >> Changes in v3: >> Split the patch as suggested by Fabio. >> >> Changes in v2: None >> >> include/configs/mx6_common.h | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h >> index e0528ce..e22336e 100644 >> --- a/include/configs/mx6_common.h >> +++ b/include/configs/mx6_common.h >> @@ -18,9 +18,12 @@ >> #define __MX6_COMMON_H >> >> #define CONFIG_ARM_ERRATA_743622 >> +#if (defined(CONFIG_MX6Q) || defined(CONFIG_MX6DL) ||\ >> +defined(CONFIG_MX6QDL)) && !defined(CONFIG_MX6S) >> #define CONFIG_ARM_ERRATA_751472 >> #define CONFIG_ARM_ERRATA_794072 >> #define CONFIG_ARM_ERRATA_761320 >> +#endif > > > > We definitely want to allow 1 binary for CONFIG_MX6DL/ CONFIG_MX6S > > so perhaps this needs to be a runtime check ? > Indeed. If static options seem to work with most of SOC, this forbids having single binary for MX6. We should use some "quirk" as in kernel to provide SOC specific fixes. I see that there is already a similar case for cp15, and there is a _weak function for it: void __weak v7_arch_cp15_set_acr(u32,.. and SOC can have there specialties there. Maybe you can add the fix as weak function in ARM code, and then in arch/arm/cpu/armv7/mx6/soc.c you can do the runtime check. Best regards, Stefano Babics
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index e0528ce..e22336e 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -18,9 +18,12 @@ #define __MX6_COMMON_H #define CONFIG_ARM_ERRATA_743622 +#if (defined(CONFIG_MX6Q) || defined(CONFIG_MX6DL) ||\ +defined(CONFIG_MX6QDL)) && !defined(CONFIG_MX6S) #define CONFIG_ARM_ERRATA_751472 #define CONFIG_ARM_ERRATA_794072 #define CONFIG_ARM_ERRATA_761320 +#endif #define CONFIG_BOARD_POSTCLK_INIT #ifndef CONFIG_SYS_L2CACHE_OFF