From patchwork Tue Feb 16 22:10:13 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 45820 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1D209B7D15 for ; Fri, 19 Feb 2010 09:55:26 +1100 (EST) Received: from localhost ([127.0.0.1]:36808 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NiFF7-0005wC-KG for incoming@patchwork.ozlabs.org; Thu, 18 Feb 2010 17:53:09 -0500 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NiF9J-0004Qq-02 for qemu-devel@nongnu.org; Thu, 18 Feb 2010 17:47:09 -0500 Received: from [199.232.76.173] (port=59362 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NiF9I-0004Q7-34 for qemu-devel@nongnu.org; Thu, 18 Feb 2010 17:47:08 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1NiF9E-00013F-UJ for qemu-devel@nongnu.org; Thu, 18 Feb 2010 17:47:07 -0500 Received: from are.twiddle.net ([75.149.56.221]:41195) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NiF9E-00012S-CX for qemu-devel@nongnu.org; Thu, 18 Feb 2010 17:47:04 -0500 Received: by are.twiddle.net (Postfix, from userid 5000) id 508D6E86; Thu, 18 Feb 2010 14:47:01 -0800 (PST) Message-Id: <407d03c79c0ef22714b39f25582a6bf93a06373c.1266533097.git.rth@twiddle.net> In-Reply-To: References: From: Richard Henderson Date: Tue, 16 Feb 2010 14:10:13 -0800 To: qemu-devel@nongnu.org X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH 3/7] tcg: Optional target implementation of ANDC. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Previously ANDC was always implemented by tcg-op.h with an explicit NOT opcode. Allow a target implementation. Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 11 +++++++++++ tcg/tcg-opc.h | 6 ++++++ 2 files changed, 17 insertions(+), 0 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 13eaa5a..447878d 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -1650,20 +1650,31 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 hi static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { +#ifdef TCG_TARGET_HAS_andc_i32 + tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2); +#else TCGv_i32 t0; t0 = tcg_temp_new_i32(); tcg_gen_not_i32(t0, arg2); tcg_gen_and_i32(ret, arg1, t0); tcg_temp_free_i32(t0); +#endif } static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { +#ifdef TCG_TARGET_HAS_andc_i64 + tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2); +#elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32 + tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); + tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); +#else TCGv_i64 t0; t0 = tcg_temp_new_i64(); tcg_gen_not_i64(t0, arg2); tcg_gen_and_i64(ret, arg1, t0); tcg_temp_free_i64(t0); +#endif } static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 89db3b4..6d855a7 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -109,6 +109,9 @@ DEF2(not_i32, 1, 1, 0, 0) #ifdef TCG_TARGET_HAS_neg_i32 DEF2(neg_i32, 1, 1, 0, 0) #endif +#ifdef TCG_TARGET_HAS_andc_i32 +DEF2(andc_i32, 1, 2, 0, 0) +#endif #if TCG_TARGET_REG_BITS == 64 DEF2(mov_i64, 1, 1, 0, 0) @@ -185,6 +188,9 @@ DEF2(not_i64, 1, 1, 0, 0) #ifdef TCG_TARGET_HAS_neg_i64 DEF2(neg_i64, 1, 1, 0, 0) #endif +#ifdef TCG_TARGET_HAS_andc_i64 +DEF2(andc_i64, 1, 2, 0, 0) +#endif #endif /* QEMU specific */