From patchwork Fri Apr 3 17:01:11 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 458002 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 225201400DE for ; Sat, 4 Apr 2015 04:07:35 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="verification failed; unprotected key" header.d=gmail.com header.i=@gmail.com header.b=cKSrpghY; dkim-adsp=none (unprotected policy); dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753693AbbDCRHd (ORCPT ); Fri, 3 Apr 2015 13:07:33 -0400 Received: from mail-wg0-f54.google.com ([74.125.82.54]:35444 "EHLO mail-wg0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752112AbbDCRCX (ORCPT ); Fri, 3 Apr 2015 13:02:23 -0400 Received: by wgdm6 with SMTP id m6so115413176wgd.2; Fri, 03 Apr 2015 10:02:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5lQNxm1PG/v9AKi72EbMzPM68Z1o31FTS6rBxoJFF5E=; b=cKSrpghYus9uPUCX2sy3/LgDMTe3au0a8Gbxe53TNlt7F0zahkkywWxmwzhyvsuy4Z 2h1GrKv24kVJ43xAkQGwMXp+1f0iGJcLek8kxmQ/5VuxbkqokDJfEy0HH0LsEBjDbOR9 9jXXNx03A+GKL3s6CBnVZ756rC+77H5NST5I+9Lfq6ZGITJpaVsRsfCFIt0MBSxjU5aK lDeM+xCrGg004MN2Ady1NUlhK48KhKjFPpRM1+3Ph+sM6OBJqf2SB3QbWqaSBvPy766K 9xywC1qnwPUdA9Y/H+6e/0RxGpmEENtDx1cqFSx7KrNXQ4chEjZBDH0NAHswoLNStF+e 79xQ== X-Received: by 10.180.83.227 with SMTP id t3mr35005669wiy.90.1428080540542; Fri, 03 Apr 2015 10:02:20 -0700 (PDT) Received: from lmecul0520.st.com. (57.26.90.92.rev.sfr.net. [92.90.26.57]) by mx.google.com with ESMTPSA id cf12sm12243851wjb.10.2015.04.03.10.02.16 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 03 Apr 2015 10:02:19 -0700 (PDT) From: Maxime Coquelin To: u.kleine-koenig@pengutronix.de, afaerber@suse.de, geert@linux-m68k.org, Rob Herring , Philipp Zabel , Linus Walleij , Arnd Bergmann , stefan@agner.ch, pmeerw@pmeerw.net, pebolle@tiscali.nl, peter@hurleysoftware.com, andy.shevchenko@gmail.com, cw00.choi@samsung.com, Russell King , Daniel Lezcano Cc: Jonathan Corbet , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Andrew Morton , "David S. Miller" , Mauro Carvalho Chehab , Joe Perches , Antti Palosaari , Tejun Heo , Will Deacon , Nikolay Borisov , Rusty Russell , Kees Cook , Michal Marek , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, mcoquelin.stm32@gmail.com Subject: [PATCH v5 05/15] dt-bindings: Document the STM32 reset bindings Date: Fri, 3 Apr 2015 19:01:11 +0200 Message-Id: <1428080481-18591-6-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1428080481-18591-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1428080481-18591-1-git-send-email-mcoquelin.stm32@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds documentation of device tree bindings for the STM32 reset controller. Tested-by: Chanwoo Choi Acked-by: Philipp Zabel Acked-by: Rob Herring Signed-off-by: Maxime Coquelin --- .../devicetree/bindings/reset/st,stm32-rcc.txt | 107 +++++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/st,stm32-rcc.txt diff --git a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt new file mode 100644 index 0000000..c1b0f8d --- /dev/null +++ b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt @@ -0,0 +1,107 @@ +STMicroelectronics STM32 Peripheral Reset Controller +==================================================== + +The RCC IP is both a reset and a clock controller. This documentation only +documents the reset part. + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "st,stm32-rcc" +- reg: should be register base and length as documented in the + datasheet +- #reset-cells: 1, see below + +example: + +rcc: reset@40023800 { + #reset-cells = <1>; + compatible = "st,stm32-rcc"; + reg = <0x40023800 0x400>; +}; + +Specifying softreset control of devices +======================================= + +Device nodes should specify the reset channel required in their "resets" +property, containing a phandle to the reset device node and an index specifying +which channel to use. +The index is the bit number within the RCC registers bank, starting from RCC +base address. +It is calculated as: index = register_offset / 4 * 32 + bit_offset. +Where bit_offset is the bit offset within the register. +For example, for CRC reset: + crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140 + +example: + + timer2 { + resets = <&rcc 256>; + }; + +List of valid indices for STM32F429: + - gpioa: 128 + - gpiob: 129 + - gpioc: 130 + - gpiod: 131 + - gpioe: 132 + - gpiof: 133 + - gpiog: 134 + - gpioh: 135 + - gpioi: 136 + - gpioj: 137 + - gpiok: 138 + - crc: 140 + - dma1: 149 + - dma2: 150 + - dma2d: 151 + - ethmac: 153 + - otghs: 157 + - dcmi: 160 + - cryp: 164 + - hash: 165 + - rng: 166 + - otgfs: 167 + - fmc: 192 + - tim2: 256 + - tim3: 257 + - tim4: 258 + - tim5: 259 + - tim6: 260 + - tim7: 261 + - tim12: 262 + - tim13: 263 + - tim14: 264 + - wwdg: 267 + - spi2: 270 + - spi3: 271 + - uart2: 273 + - uart3: 274 + - uart4: 275 + - uart5: 276 + - i2c1: 277 + - i2c2: 278 + - i2c3: 279 + - can1: 281 + - can2: 282 + - pwr: 284 + - dac: 285 + - uart7: 286 + - uart8: 287 + - tim1: 288 + - tim8: 289 + - usart1: 292 + - usart6: 293 + - adc: 296 + - sdio: 299 + - spi1: 300 + - spi4: 301 + - syscfg: 302 + - tim9: 304 + - tim10: 305 + - tim11: 306 + - spi5: 308 + - spi6: 309 + - sai1: 310 + - ltdc: 314