Message ID | 1427993406-21323-1-git-send-email-heshamelmatary@gmail.com |
---|---|
State | New |
Headers | show |
On 04/02/2015 09:50 AM, Hesham ALMatary wrote: > or1ksim simulator currently handles "l.nop 0xC" instruction as > a halt signal. Do the same for QEMU. > > Signed-off-by: Hesham ALMatary <heshamelmatary@gmail.com> > --- > target-openrisc/translate.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c > index dc76789..5fa8ede 100644 > --- a/target-openrisc/translate.c > +++ b/target-openrisc/translate.c > @@ -750,6 +750,11 @@ static void dec_misc(DisasContext *dc, uint32_t insn) > switch (op1) { > case 0x01: /* l.nop */ > LOG_DIS("l.nop %d\n", I16); > + > + if(I16 == 0xC) { > + exit(0); > + } > + Ug. IMO l.nop was a poor choice; l.trap would have been better. But whatever... Further: (1) This is translation time, not execution time. You can't do the exit here, only when the instruction is executed. (2) This, and the other 10 things hidden under l_nop are similar to the "-semihosting" switch available for arm, lm32, m68k, and xtensa. Although semihosting is typically even more complex, generally implementing the exit/read/write/open/close/lseek/stat families of syscalls. r~
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index dc76789..5fa8ede 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -750,6 +750,11 @@ static void dec_misc(DisasContext *dc, uint32_t insn) switch (op1) { case 0x01: /* l.nop */ LOG_DIS("l.nop %d\n", I16); + + if(I16 == 0xC) { + exit(0); + } + break; default:
or1ksim simulator currently handles "l.nop 0xC" instruction as a halt signal. Do the same for QEMU. Signed-off-by: Hesham ALMatary <heshamelmatary@gmail.com> --- target-openrisc/translate.c | 5 +++++ 1 file changed, 5 insertions(+)