| Message ID | 1427437416-25202-4-git-send-email-voice.shen@atmel.com |
|---|---|
| State | Accepted, archived |
| Delegated to: | Andreas Bießmann |
| Headers | show |
Dear Bo Shen, Bo Shen <voice.shen@atmel.com> writes: >Enable SPL support for at91sam9x5ek board. Now, it supports >boot up from NAND flash and SPI flash. > >Signed-off-by: Bo Shen <voice.shen@atmel.com> >--- > >Changes in v2: > - Remove the meaningless prefix "+S:" in configuration file. > > arch/arm/mach-at91/Kconfig | 1 + > arch/arm/mach-at91/Makefile | 1 + > arch/arm/mach-at91/include/mach/at91_pmc.h | 6 ++- > arch/arm/mach-at91/include/mach/at91sam9x5.h | 10 ++++ > arch/arm/mach-at91/mpddrc.c | 3 +- > arch/arm/mach-at91/spl.c | 2 +- > arch/arm/mach-at91/spl_at91.c | 5 ++ > board/atmel/at91sam9x5ek/at91sam9x5ek.c | 74 ++++++++++++++++++++++++++++ > configs/at91sam9x5ek_nandflash_defconfig | 1 + > configs/at91sam9x5ek_spiflash_defconfig | 1 + > include/configs/at91sam9x5ek.h | 57 +++++++++++++++++++++ > 11 files changed, 157 insertions(+), 4 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann
Hi Eugene, Hi Bo, On 27.03.15 07:23, Bo Shen wrote: > Enable SPL support for at91sam9x5ek board. Now, it supports > boot up from NAND flash and SPI flash. > > Signed-off-by: Bo Shen <voice.shen@atmel.com> Sorry to hijack this thread, but I do have a few questions here. I'm currently working on a mainline port for a custom board based on the CORE9G25 SoM [1] and would like to use U-Boot SPL instead of AT91Bootstrap. In this email, you "enable spl support" as stated in the commit subject, but CONFIG_SPL is not enabled for this board at any time. So only the code is present to e.g. init the DDR2 but its actually not executed. Or am I missing something here. Could you please let me know, what the status of this SPL support for the AT91SAM9X5 is? Has this been tested without AT91Bootstrap lately? Thanks, Stefan [1] www.armdevs.com/CORE9G25.html > --- > > Changes in v2: > - Remove the meaningless prefix "+S:" in configuration file. > > arch/arm/mach-at91/Kconfig | 1 + > arch/arm/mach-at91/Makefile | 1 + > arch/arm/mach-at91/include/mach/at91_pmc.h | 6 ++- > arch/arm/mach-at91/include/mach/at91sam9x5.h | 10 ++++ > arch/arm/mach-at91/mpddrc.c | 3 +- > arch/arm/mach-at91/spl.c | 2 +- > arch/arm/mach-at91/spl_at91.c | 5 ++ > board/atmel/at91sam9x5ek/at91sam9x5ek.c | 74 ++++++++++++++++++++++++++++ > configs/at91sam9x5ek_nandflash_defconfig | 1 + > configs/at91sam9x5ek_spiflash_defconfig | 1 + > include/configs/at91sam9x5ek.h | 57 +++++++++++++++++++++ > 11 files changed, 157 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig > index 25da926..bdf87f9 100644 > --- a/arch/arm/mach-at91/Kconfig > +++ b/arch/arm/mach-at91/Kconfig > @@ -83,6 +83,7 @@ config TARGET_AT91SAM9RLEK > config TARGET_AT91SAM9X5EK > bool "Atmel AT91SAM9X5-EK board" > select CPU_ARM926EJS > + select SUPPORT_SPL > > config TARGET_SAMA5D3_XPLAINED > bool "SAMA5D3 Xplained board" > diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile > index e596ba6..ba83616 100644 > --- a/arch/arm/mach-at91/Makefile > +++ b/arch/arm/mach-at91/Makefile > @@ -2,6 +2,7 @@ obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o > ifneq ($(CONFIG_SPL_BUILD),) > obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o > obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o > +obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o > obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o > obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o > obj-y += spl.o > diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h > index 65691ab..c903260 100644 > --- a/arch/arm/mach-at91/include/mach/at91_pmc.h > +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h > @@ -97,7 +97,8 @@ typedef struct at91_pmc { > #define AT91_PMC_MCKR_CSS_PLLB 0x00000003 > #define AT91_PMC_MCKR_CSS_MASK 0x00000003 > > -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) > +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ > + defined(CONFIG_AT91SAM9X5) > #define AT91_PMC_MCKR_PRES_1 0x00000000 > #define AT91_PMC_MCKR_PRES_2 0x00000010 > #define AT91_PMC_MCKR_PRES_4 0x00000020 > @@ -126,7 +127,8 @@ typedef struct at91_pmc { > #else > #define AT91_PMC_MCKR_MDIV_1 0x00000000 > #define AT91_PMC_MCKR_MDIV_2 0x00000100 > -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) > +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ > + defined(CONFIG_AT91SAM9X5) > #define AT91_PMC_MCKR_MDIV_3 0x00000300 > #endif > #define AT91_PMC_MCKR_MDIV_4 0x00000200 > diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h > index 36a5cdf..d18c936 100644 > --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h > +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h > @@ -124,6 +124,16 @@ > #define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */ > #endif > > +/* > + * External memory > + */ > +#define ATMEL_BASE_CS0 0x10000000 > +#define ATMEL_BASE_CS1 0x20000000 > +#define ATMEL_BASE_CS2 0x30000000 > +#define ATMEL_BASE_CS3 0x40000000 > +#define ATMEL_BASE_CS4 0x50000000 > +#define ATMEL_BASE_CS5 0x60000000 > + > /* 9x5 series chip id definitions */ > #define ARCH_ID_AT91SAM9X5 0x819a05a0 > #define ARCH_ID_VERSION_MASK 0x1f > diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c > index beec13d..24d5fcd 100644 > --- a/arch/arm/mach-at91/mpddrc.c > +++ b/arch/arm/mach-at91/mpddrc.c > @@ -19,7 +19,8 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address) > > static int ddr2_decodtype_is_seq(u32 cr) > { > -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) > +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ > + defined(CONFIG_AT91SAM9X5) > if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED) > return 0; > #endif > diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c > index aaa5eec..27a405a 100644 > --- a/arch/arm/mach-at91/spl.c > +++ b/arch/arm/mach-at91/spl.c > @@ -29,7 +29,7 @@ u32 spl_boot_device(void) > return BOOT_DEVICE_MMC1; > #elif CONFIG_SYS_USE_NANDFLASH > return BOOT_DEVICE_NAND; > -#elif CONFIG_SYS_USE_SERIALFLASH > +#elif CONFIG_SYS_USE_SERIALFLASH || CONFIG_SYS_USE_SPIFLASH > return BOOT_DEVICE_SPI; > #endif > return BOOT_DEVICE_NONE; > diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c > index af6fc0d..e28e568 100644 > --- a/arch/arm/mach-at91/spl_at91.c > +++ b/arch/arm/mach-at91/spl_at91.c > @@ -115,9 +115,14 @@ void board_init_f(ulong dummy) > timer_init(); > > /* enable clocks for all PIOs */ > +#ifdef CONFIG_AT91SAM9X5 > + at91_periph_clk_enable(ATMEL_ID_PIOAB); > + at91_periph_clk_enable(ATMEL_ID_PIOCD); > +#else > at91_periph_clk_enable(ATMEL_ID_PIOA); > at91_periph_clk_enable(ATMEL_ID_PIOB); > at91_periph_clk_enable(ATMEL_ID_PIOC); > +#endif > /* init console */ > at91_seriald_hw_init(); > preloader_console_init(); > diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c > index 17a2a40..114ac5c 100644 > --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c > +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c > @@ -293,3 +293,77 @@ int dram_init(void) > CONFIG_SYS_SDRAM_SIZE); > return 0; > } > + > +#if defined(CONFIG_SPL_BUILD) > +#include <spl.h> > +#include <nand.h> > + > +void at91_spl_board_init(void) > +{ > +#ifdef CONFIG_SYS_USE_MMC > + at91_mci_hw_init(); > +#elif CONFIG_SYS_USE_NANDFLASH > + at91sam9x5ek_nand_hw_init(); > +#elif CONFIG_SYS_USE_SPIFLASH > + at91_spi0_hw_init(1 << 4); > +#endif > +} > + > +#include <asm/arch/atmel_mpddrc.h> > +static void ddr2_conf(struct atmel_mpddr *ddr2) > +{ > + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); > + > + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | > + ATMEL_MPDDRC_CR_NR_ROW_13 | > + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | > + ATMEL_MPDDRC_CR_NB_8BANKS | > + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED); > + > + ddr2->rtr = 0x411; > + > + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | > + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | > + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | > + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | > + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | > + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | > + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | > + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); > + > + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | > + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | > + 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | > + 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); > + > + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | > + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | > + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | > + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | > + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); > +} > + > +void mem_init(void) > +{ > + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; > + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; > + struct atmel_mpddr ddr2; > + unsigned long csa; > + > + ddr2_conf(&ddr2); > + > + /* enable DDR2 clock */ > + writel(0x4, &pmc->scer); > + > + /* Chip select 1 is for DDR2/SDRAM */ > + csa = readl(&matrix->ebicsa); > + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; > + csa &= ~AT91_MATRIX_EBI_DBPU_OFF; > + csa |= AT91_MATRIX_EBI_DBPD_OFF; > + csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; > + writel(csa, &matrix->ebicsa); > + > + /* DDRAM2 Controller initialize */ > + ddr2_init(ATMEL_BASE_CS1, &ddr2); > +} > +#endif > diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig > index c2ebb00..6eea1af 100644 > --- a/configs/at91sam9x5ek_nandflash_defconfig > +++ b/configs/at91sam9x5ek_nandflash_defconfig > @@ -1,3 +1,4 @@ > +CONFIG_SPL=y > CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH" > CONFIG_ARM=y > CONFIG_ARCH_AT91=y > diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig > index 76f68a6..7ef1534 100644 > --- a/configs/at91sam9x5ek_spiflash_defconfig > +++ b/configs/at91sam9x5ek_spiflash_defconfig > @@ -1,3 +1,4 @@ > +CONFIG_SPL=y > CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH" > CONFIG_ARM=y > CONFIG_ARCH_AT91=y > diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h > index 6d8b71d..1a481b3 100644 > --- a/include/configs/at91sam9x5ek.h > +++ b/include/configs/at91sam9x5ek.h > @@ -243,4 +243,61 @@ > */ > #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) > > +/* SPL */ > +#define CONFIG_SPL_FRAMEWORK > +#define CONFIG_SPL_TEXT_BASE 0x300000 > +#define CONFIG_SPL_MAX_SIZE 0x6000 > +#define CONFIG_SPL_STACK 0x308000 > + > +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 > +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 > +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 > + > +#define CONFIG_SPL_LIBCOMMON_SUPPORT > +#define CONFIG_SPL_LIBGENERIC_SUPPORT > +#define CONFIG_SPL_GPIO_SUPPORT > +#define CONFIG_SPL_SERIAL_SUPPORT > + > +#define CONFIG_SPL_BOARD_INIT > +#define CONFIG_SYS_MONITOR_LEN (512 << 10) > + > +#define CONFIG_SYS_MASTER_CLOCK 132096000 > +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 > +#define CONFIG_SYS_MCKR 0x1301 > +#define CONFIG_SYS_MCKR_CSS 0x1302 > + > +#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC > + > +#ifdef CONFIG_SYS_USE_MMC > +#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds > +#define CONFIG_SPL_MMC_SUPPORT > +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 > +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 > +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" > +#define CONFIG_SPL_FAT_SUPPORT > +#define CONFIG_SPL_LIBDISK_SUPPORT > + > +#elif CONFIG_SYS_USE_NANDFLASH > +#define CONFIG_SPL_NAND_SUPPORT > +#define CONFIG_SPL_NAND_DRIVERS > +#define CONFIG_SPL_NAND_BASE > +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 > +#define CONFIG_SYS_NAND_5_ADDR_CYCLE > +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 > +#define CONFIG_SYS_NAND_PAGE_COUNT 64 > +#define CONFIG_SYS_NAND_OOBSIZE 64 > +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 > +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 > +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER > + > +#elif CONFIG_SYS_USE_SPIFLASH > +#define CONFIG_SPL_SPI_SUPPORT > +#define CONFIG_SPL_SPI_FLASH_SUPPORT > +#define CONFIG_SPL_SPI_LOAD > +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 > + > +#endif > + > #endif > Viele Grüße, Stefan
On 19.02.2019 15:27, Stefan Roese wrote: > Hi Eugene, > Hi Bo, > > On 27.03.15 07:23, Bo Shen wrote: >> Enable SPL support for at91sam9x5ek board. Now, it supports >> boot up from NAND flash and SPI flash. >> >> Signed-off-by: Bo Shen <voice.shen@atmel.com> > > Sorry to hijack this thread, but I do have a few questions here. > > I'm currently working on a mainline port for a custom board > based on the CORE9G25 SoM [1] and would like to use U-Boot SPL > instead of AT91Bootstrap. In this email, you "enable spl support" > as stated in the commit subject, but CONFIG_SPL is not enabled > for this board at any time. So only the code is present to e.g. > init the DDR2 but its actually not executed. Or am I missing > something here. > > Could you please let me know, what the status of this SPL > support for the AT91SAM9X5 is? Has this been tested without > AT91Bootstrap lately? Hi, I did not test myself the SPL for any 9x5 board. The DDR2 init code should be executed inside the SPL. Once you build your board with a CONFIG_SPL enabled, you should get the spl binary built, then you can add both SPL + U-boot proper on the boot media and have SPL boot (execute DDR init code and load U-boot proper). I would suggest to try on Sd-card first because it's easier (filesystem), but the commit says only SPI and NAND tested. You can also look at the U-boot version which first included this patch, some things may have changed since... Let me know of your findings. I will let you know if I have the chance to test this myself. Eugen > > Thanks, > Stefan > > [1] www.armdevs.com/CORE9G25.html > >> --- [...]
Hi Eugene, On 19.02.19 15:12, Eugen.Hristev@microchip.com wrote: > On 19.02.2019 15:27, Stefan Roese wrote: >> Hi Eugene, >> Hi Bo, >> >> On 27.03.15 07:23, Bo Shen wrote: >>> Enable SPL support for at91sam9x5ek board. Now, it supports >>> boot up from NAND flash and SPI flash. >>> >>> Signed-off-by: Bo Shen <voice.shen@atmel.com> >> >> Sorry to hijack this thread, but I do have a few questions here. >> >> I'm currently working on a mainline port for a custom board >> based on the CORE9G25 SoM [1] and would like to use U-Boot SPL >> instead of AT91Bootstrap. In this email, you "enable spl support" >> as stated in the commit subject, but CONFIG_SPL is not enabled >> for this board at any time. So only the code is present to e.g. >> init the DDR2 but its actually not executed. Or am I missing >> something here. >> >> Could you please let me know, what the status of this SPL >> support for the AT91SAM9X5 is? Has this been tested without >> AT91Bootstrap lately? > > > Hi, > > I did not test myself the SPL for any 9x5 board. The DDR2 init code > should be executed inside the SPL. Once you build your board with a > CONFIG_SPL enabled, you should get the spl binary built, then you can > add both SPL + U-boot proper on the boot media and have SPL boot > (execute DDR init code and load U-boot proper). I would suggest to try > on Sd-card first because it's easier (filesystem), but the commit says > only SPI and NAND tested. On this board I only have NAND, so there is no option to first test some other boot device unfortunately. > You can also look at the U-boot version which first included this patch, > some things may have changed since... Sure, I can and will check this. But I first wanted to check with you guys about the status, since you implemented and most likely also tested this stuff. > Let me know of your findings. I will let you know if I have the chance > to test this myself. Okay. I'll try to test this stuff (even though I don't have JTAG on this board) and will get back to you with findings and most likely also some further questions. Thanks, Stefan
Hi Eugene, On 19.02.19 15:56, Stefan Roese wrote: <snip> >> I did not test myself the SPL for any 9x5 board. The DDR2 init code >> should be executed inside the SPL. Once you build your board with a >> CONFIG_SPL enabled, you should get the spl binary built, then you can >> add both SPL + U-boot proper on the boot media and have SPL boot >> (execute DDR init code and load U-boot proper). I would suggest to try >> on Sd-card first because it's easier (filesystem), but the commit says >> only SPI and NAND tested. > > On this board I only have NAND, so there is no option to first test > some other boot device unfortunately. > >> You can also look at the U-boot version which first included this patch, >> some things may have changed since... > > Sure, I can and will check this. But I first wanted to check with > you guys about the status, since you implemented and most likely > also tested this stuff. > >> Let me know of your findings. I will let you know if I have the chance >> to test this myself. > > Okay. I'll try to test this stuff (even though I don't have JTAG on > this board) and will get back to you with findings and most likely > also some further questions. So I did make some progress here but building and testing the SPL version by loading it to 0x30.0000 and starting it there via the "go" command. I'm not brave enough to flash it right now, since de-bricking might be tricky here, as I don't have JTAG. With the loaded version I'm able to fully load the main U-Boot image from NAND and run it from there to the prompt. But then I looked at the latest AT91Bootstrap code and noticed the many changes in the lowlevel boot code (clocking, DDR2, etc). I'm a bit hesitant to port all this code to mainline U-Boot SPL here. One reason being that you at Microchip / Atmel will most likely continue to work on the AT91Bootstrap code and not on the potentially ported SPL code version. So what's you opinion here on this? Why do you not integrate all this code into U-Boot SPL and drop this bootstrap version completely? What is your suggestion for me on how to handle this? Stay with AT91Bootstrap or move to SPL? Thanks, Stefan
On 21.02.2019 19:00, Stefan Roese wrote: > Hi Eugene, > > On 19.02.19 15:56, Stefan Roese wrote: > > <snip> > >>> I did not test myself the SPL for any 9x5 board. The DDR2 init code >>> should be executed inside the SPL. Once you build your board with a >>> CONFIG_SPL enabled, you should get the spl binary built, then you can >>> add both SPL + U-boot proper on the boot media and have SPL boot >>> (execute DDR init code and load U-boot proper). I would suggest to try >>> on Sd-card first because it's easier (filesystem), but the commit says >>> only SPI and NAND tested. >> >> On this board I only have NAND, so there is no option to first test >> some other boot device unfortunately. >> >>> You can also look at the U-boot version which first included this patch, >>> some things may have changed since... >> >> Sure, I can and will check this. But I first wanted to check with >> you guys about the status, since you implemented and most likely >> also tested this stuff. >>> Let me know of your findings. I will let you know if I have the chance >>> to test this myself. >> >> Okay. I'll try to test this stuff (even though I don't have JTAG on >> this board) and will get back to you with findings and most likely >> also some further questions. > > So I did make some progress here but building and testing the SPL > version by loading it to 0x30.0000 and starting it there via the > "go" command. I'm not brave enough to flash it right now, since > de-bricking might be tricky here, as I don't have JTAG. With the > loaded version I'm able to fully load the main U-Boot image from > NAND and run it from there to the prompt. Hi Stefan, Send me a patch and I can apply and test, but I cannot promise to have it very fast :) (or your git tree from where I can pull...) Have to make it for 9x5-ek board, as I do not have anything else at my disposal > > But then I looked at the latest AT91Bootstrap code and noticed the > many changes in the lowlevel boot code (clocking, DDR2, etc). I'm > a bit hesitant to port all this code to mainline U-Boot SPL here. > One reason being that you at Microchip / Atmel will most likely > continue to work on the AT91Bootstrap code and not on the > potentially ported SPL code version. So what's you opinion here on > this? Why do you not integrate all this code into U-Boot SPL and > drop this bootstrap version completely? What is your suggestion for > me on how to handle this? Stay with AT91Bootstrap or move to SPL? At91boostrap is always recommended as we have the latest implementation and it's used by most of the people using at91 boards and more tested. We always try to keep SPL in sync , but it's only on best-effort at this moment I will review/take patches for SPL of course. There are people who use it so we try to have it working at all times. Eugen > > Thanks, > Stefan >
Hi Eugene, On 22.02.19 16:57, Eugen.Hristev@microchip.com wrote: > > > On 21.02.2019 19:00, Stefan Roese wrote: >> Hi Eugene, >> >> On 19.02.19 15:56, Stefan Roese wrote: >> >> <snip> >> >>>> I did not test myself the SPL for any 9x5 board. The DDR2 init code >>>> should be executed inside the SPL. Once you build your board with a >>>> CONFIG_SPL enabled, you should get the spl binary built, then you can >>>> add both SPL + U-boot proper on the boot media and have SPL boot >>>> (execute DDR init code and load U-boot proper). I would suggest to try >>>> on Sd-card first because it's easier (filesystem), but the commit says >>>> only SPI and NAND tested. >>> >>> On this board I only have NAND, so there is no option to first test >>> some other boot device unfortunately. >>> >>>> You can also look at the U-boot version which first included this patch, >>>> some things may have changed since... >>> >>> Sure, I can and will check this. But I first wanted to check with >>> you guys about the status, since you implemented and most likely >>> also tested this stuff. >>>> Let me know of your findings. I will let you know if I have the chance >>>> to test this myself. >>> >>> Okay. I'll try to test this stuff (even though I don't have JTAG on >>> this board) and will get back to you with findings and most likely >>> also some further questions. >> >> So I did make some progress here but building and testing the SPL >> version by loading it to 0x30.0000 and starting it there via the >> "go" command. I'm not brave enough to flash it right now, since >> de-bricking might be tricky here, as I don't have JTAG. With the >> loaded version I'm able to fully load the main U-Boot image from >> NAND and run it from there to the prompt. > > Hi Stefan, > > Send me a patch and I can apply and test, but I cannot promise to have > it very fast :) (or your git tree from where I can pull...) > Have to make it for 9x5-ek board, as I do not have anything else at my > disposal I might come back to your offer, thanks! > >> >> But then I looked at the latest AT91Bootstrap code and noticed the >> many changes in the lowlevel boot code (clocking, DDR2, etc). I'm >> a bit hesitant to port all this code to mainline U-Boot SPL here. >> One reason being that you at Microchip / Atmel will most likely >> continue to work on the AT91Bootstrap code and not on the >> potentially ported SPL code version. So what's you opinion here on >> this? Why do you not integrate all this code into U-Boot SPL and >> drop this bootstrap version completely? What is your suggestion for >> me on how to handle this? Stay with AT91Bootstrap or move to SPL? > > At91boostrap is always recommended as we have the latest implementation > and it's used by most of the people using at91 boards and more tested. I see. The decision to completely move to SPL should have probably been made some years ago then (as other SoC vendors have done). Nothing to be done about this now. Still, what I really like in this SPL approach vs the vendor pre U-Boot loader is, that all is encapsulated in one source code repository and one image usually is generated, simplifying the bootloader building and programming quite a bit. > We always try to keep SPL in sync , but it's only on best-effort at this > moment > I will review/take patches for SPL of course. There are people who use > it so we try to have it working at all times. Okay, good to know. Thanks, Stefan
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 25da926..bdf87f9 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -83,6 +83,7 @@ config TARGET_AT91SAM9RLEK config TARGET_AT91SAM9X5EK bool "Atmel AT91SAM9X5-EK board" select CPU_ARM926EJS + select SUPPORT_SPL config TARGET_SAMA5D3_XPLAINED bool "SAMA5D3 Xplained board" diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index e596ba6..ba83616 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o ifneq ($(CONFIG_SPL_BUILD),) obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o +obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o obj-y += spl.o diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 65691ab..c903260 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -97,7 +97,8 @@ typedef struct at91_pmc { #define AT91_PMC_MCKR_CSS_PLLB 0x00000003 #define AT91_PMC_MCKR_CSS_MASK 0x00000003 -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ + defined(CONFIG_AT91SAM9X5) #define AT91_PMC_MCKR_PRES_1 0x00000000 #define AT91_PMC_MCKR_PRES_2 0x00000010 #define AT91_PMC_MCKR_PRES_4 0x00000020 @@ -126,7 +127,8 @@ typedef struct at91_pmc { #else #define AT91_PMC_MCKR_MDIV_1 0x00000000 #define AT91_PMC_MCKR_MDIV_2 0x00000100 -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ + defined(CONFIG_AT91SAM9X5) #define AT91_PMC_MCKR_MDIV_3 0x00000300 #endif #define AT91_PMC_MCKR_MDIV_4 0x00000200 diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index 36a5cdf..d18c936 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h @@ -124,6 +124,16 @@ #define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */ #endif +/* + * External memory + */ +#define ATMEL_BASE_CS0 0x10000000 +#define ATMEL_BASE_CS1 0x20000000 +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 +#define ATMEL_BASE_CS4 0x50000000 +#define ATMEL_BASE_CS5 0x60000000 + /* 9x5 series chip id definitions */ #define ARCH_ID_AT91SAM9X5 0x819a05a0 #define ARCH_ID_VERSION_MASK 0x1f diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c index beec13d..24d5fcd 100644 --- a/arch/arm/mach-at91/mpddrc.c +++ b/arch/arm/mach-at91/mpddrc.c @@ -19,7 +19,8 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address) static int ddr2_decodtype_is_seq(u32 cr) { -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ + defined(CONFIG_AT91SAM9X5) if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED) return 0; #endif diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c index aaa5eec..27a405a 100644 --- a/arch/arm/mach-at91/spl.c +++ b/arch/arm/mach-at91/spl.c @@ -29,7 +29,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_MMC1; #elif CONFIG_SYS_USE_NANDFLASH return BOOT_DEVICE_NAND; -#elif CONFIG_SYS_USE_SERIALFLASH +#elif CONFIG_SYS_USE_SERIALFLASH || CONFIG_SYS_USE_SPIFLASH return BOOT_DEVICE_SPI; #endif return BOOT_DEVICE_NONE; diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index af6fc0d..e28e568 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -115,9 +115,14 @@ void board_init_f(ulong dummy) timer_init(); /* enable clocks for all PIOs */ +#ifdef CONFIG_AT91SAM9X5 + at91_periph_clk_enable(ATMEL_ID_PIOAB); + at91_periph_clk_enable(ATMEL_ID_PIOCD); +#else at91_periph_clk_enable(ATMEL_ID_PIOA); at91_periph_clk_enable(ATMEL_ID_PIOB); at91_periph_clk_enable(ATMEL_ID_PIOC); +#endif /* init console */ at91_seriald_hw_init(); preloader_console_init(); diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 17a2a40..114ac5c 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -293,3 +293,77 @@ int dram_init(void) CONFIG_SYS_SDRAM_SIZE); return 0; } + +#if defined(CONFIG_SPL_BUILD) +#include <spl.h> +#include <nand.h> + +void at91_spl_board_init(void) +{ +#ifdef CONFIG_SYS_USE_MMC + at91_mci_hw_init(); +#elif CONFIG_SYS_USE_NANDFLASH + at91sam9x5ek_nand_hw_init(); +#elif CONFIG_SYS_USE_SPIFLASH + at91_spi0_hw_init(1 << 4); +#endif +} + +#include <asm/arch/atmel_mpddrc.h> +static void ddr2_conf(struct atmel_mpddr *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_13 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED); + + ddr2->rtr = 0x411; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct atmel_mpddr ddr2; + unsigned long csa; + + ddr2_conf(&ddr2); + + /* enable DDR2 clock */ + writel(0x4, &pmc->scer); + + /* Chip select 1 is for DDR2/SDRAM */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; + csa &= ~AT91_MATRIX_EBI_DBPU_OFF; + csa |= AT91_MATRIX_EBI_DBPD_OFF; + csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; + writel(csa, &matrix->ebicsa); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_CS1, &ddr2); +} +#endif diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index c2ebb00..6eea1af 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -1,3 +1,4 @@ +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index 76f68a6..7ef1534 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -1,3 +1,4 @@ +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 6d8b71d..1a481b3 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -243,4 +243,61 @@ */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE 0x6000 +#define CONFIG_SPL_STACK 0x308000 + +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT + +#elif CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER + +#elif CONFIG_SYS_USE_SPIFLASH +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 + +#endif + #endif
Enable SPL support for at91sam9x5ek board. Now, it supports boot up from NAND flash and SPI flash. Signed-off-by: Bo Shen <voice.shen@atmel.com> --- Changes in v2: - Remove the meaningless prefix "+S:" in configuration file. arch/arm/mach-at91/Kconfig | 1 + arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/include/mach/at91_pmc.h | 6 ++- arch/arm/mach-at91/include/mach/at91sam9x5.h | 10 ++++ arch/arm/mach-at91/mpddrc.c | 3 +- arch/arm/mach-at91/spl.c | 2 +- arch/arm/mach-at91/spl_at91.c | 5 ++ board/atmel/at91sam9x5ek/at91sam9x5ek.c | 74 ++++++++++++++++++++++++++++ configs/at91sam9x5ek_nandflash_defconfig | 1 + configs/at91sam9x5ek_spiflash_defconfig | 1 + include/configs/at91sam9x5ek.h | 57 +++++++++++++++++++++ 11 files changed, 157 insertions(+), 4 deletions(-)