From patchwork Sun Feb 14 18:32:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [3/3] target-arm: support thumb exception handlers Date: Sun, 14 Feb 2010 08:32:36 -0000 From: Rabin Vincent X-Patchwork-Id: 45334 Message-Id: <1266172357-9252-4-git-send-email-rabin@rab.in> To: qemu-devel@nongnu.org Cc: Rabin Vincent When handling an exception, switch to the correct mode based on the Thumb Exception (TE) bit in the SCTLR. Signed-off-by: Rabin Vincent --- target-arm/helper.c | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 27001e8..434628b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -824,11 +824,10 @@ void do_interrupt(CPUARMState *env) env->spsr = cpsr_read(env); /* Clear IT bits. */ env->condexec_bits = 0; - /* Switch to the new mode, and switch to Arm mode. */ - /* ??? Thumb interrupt handlers not implemented. */ + /* Switch to the new mode, and to the correct instruction set. */ env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; env->uncached_cpsr |= mask; - env->thumb = 0; + env->thumb = !!(env->cp15.c1_sys & (1 << 30)); env->regs[14] = env->regs[15] + offset; env->regs[15] = addr; env->interrupt_request |= CPU_INTERRUPT_EXITTB;