From patchwork Wed Mar 18 10:51:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 451370 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id A607014009B for ; Wed, 18 Mar 2015 21:52:53 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755998AbbCRKv4 (ORCPT ); Wed, 18 Mar 2015 06:51:56 -0400 Received: from mail-we0-f174.google.com ([74.125.82.174]:36702 "EHLO mail-we0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753969AbbCRKvw (ORCPT ); Wed, 18 Mar 2015 06:51:52 -0400 Received: by wetk59 with SMTP id k59so28928416wet.3 for ; Wed, 18 Mar 2015 03:51:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qFOP4xDTSft0Vn47wR2AF0f2cogwVKck9dkMg7Kj48s=; b=cU9kQyO3uoI+kzasRk/8ooeas+0o1QeuakELiWciv8fWpX+ORgMYP6AprXyNFowGIi FHPwqwOwSh9imgQKjhvCPYKXkaCuMV9gDbasfIS+0C6CHeHw9lSeB31wAjx92vMNRywe EpruOqV35TXjrhxwlpptDs/dH/J5/+IeE50UrvbZTERJF3NAL8A+6Q+/HXfSVQF+875C qh3vLNHVdi2I4rZxBakgJUXg4180L1BYfb3iEc+DgNGYeLmMg03llVPeasiZr5JlQK6p zlQMIIid6NRSlJWWAqX2FLwefDD3i3xnQLB/rqF9/UqFn2cAognP5k2DgAU3D9+7P1Nb eryA== X-Gm-Message-State: ALoCoQlqW+kjW47u3UVwdi9EeFA9rrLo1/PPvQLuG9pNN0lG6yKHGBlvhj8uzmLBGe8n4/CNikir X-Received: by 10.180.77.199 with SMTP id u7mr5851648wiw.42.1426675910870; Wed, 18 Mar 2015 03:51:50 -0700 (PDT) Received: from localhost.localdomain ([81.134.86.251]) by mx.google.com with ESMTPSA id gz3sm2665532wib.1.2015.03.18.03.51.49 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Mar 2015 03:51:50 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, linux-gpio@vger.kernel.org Cc: lee.jones@linaro.org, kernel@stlinux.com, Karim BEN BELGACEM Subject: [PATCH 1/6] ARM: STi: DT: STiH407: Fix retime pin mask for PIO5 and PIO35 Date: Wed, 18 Mar 2015 10:51:34 +0000 Message-Id: <1426675899-19882-2-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1426675899-19882-1-git-send-email-lee.jones@linaro.org> References: <1426675899-19882-1-git-send-email-lee.jones@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Karim BEN BELGACEM This will avoid programming the retime registers when not implemented - PIO5 : no retime registers assigned to pins 6 and 7 - PIO35 : pin 7 is reserved so no retime register assigned to it Signed-off-by: Karim BEN BELGACEM Signed-off-by: Lee Jones Acked-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index 402844c..0a754f2 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -104,6 +104,7 @@ #interrupt-cells = <2>; reg = <0x5000 0x100>; st,bank-name = "PIO5"; + st,retime-pin-mask = <0x3f>; }; rc { @@ -519,6 +520,7 @@ #interrupt-cells = <2>; reg = <0x5000 0x100>; st,bank-name = "PIO35"; + st,retime-pin-mask = <0x7f>; }; i2c4 {