From patchwork Mon Mar 16 14:20:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel Fernandez X-Patchwork-Id: 450596 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D6A69140083 for ; Tue, 17 Mar 2015 01:44:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965067AbbCPOo1 (ORCPT ); Mon, 16 Mar 2015 10:44:27 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:34671 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965058AbbCPOZC (ORCPT ); Mon, 16 Mar 2015 10:25:02 -0400 Received: from pps.filterd (m0046670.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.14.5/8.14.5) with SMTP id t2GEMFul015341; Mon, 16 Mar 2015 15:22:58 +0100 Received: from beta.dmz-us.st.com (beta.dmz-us.st.com [167.4.1.35]) by mx07-00178001.pphosted.com with ESMTP id 1t4hukujws-1 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 16 Mar 2015 15:22:58 +0100 Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 00DE72E; Mon, 16 Mar 2015 14:21:15 +0000 (GMT) Received: from mail7.sgp.st.com (unknown [164.129.223.81]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id 1F7AC2F; Mon, 16 Mar 2015 14:21:09 +0000 (GMT) Received: from lmenx315.lme.st.com ([10.48.254.186]) by mail7.sgp.st.com (MOS 4.3.3-GA) with ESMTP id BZT43684 (AUTH frq07381); Mon, 16 Mar 2015 15:20:54 +0100 From: Gabriel FERNANDEZ To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Bjorn Helgaas , Mohit Kumar , Jingoo Han , Lucas Stach , Fabrice Gasnier , Kishon Vijay Abraham I , Andrew Morton , " David S. Miller" , Greg KH , Mauro Carvalho Chehab , Joe Perches , Tejun Heo , Arnd Bergmann , Viresh Kumar , Thierry Reding , Phil Edworthy , Minghuan Lian , Tanmay Inamdar , , Sachin Kamat , Andrew Lunn , Liviu Dudau Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@stlinux.com, linux-pci@vger.kernel.org, Lee Jones , Gabriel Fernandez Subject: [PATCH v2 4/5] PCI: designware: Add disable IO support Date: Mon, 16 Mar 2015 15:20:34 +0100 Message-Id: <1426515635-9466-5-git-send-email-gabriel.fernandez@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1426515635-9466-1-git-send-email-gabriel.fernandez@linaro.org> References: <1426515635-9466-1-git-send-email-gabriel.fernandez@linaro.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.13.68, 1.0.33, 0.0.0000 definitions=2015-03-16_01:2015-03-13, 2015-03-15, 1970-01-01 signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org ST sti SoCs PCIe IPs are built around DesignWare IP Core. But in these SoCs PCIe IP doesn't support IO. This patch adds the possibility to disable it through a DT property, by creating an empty IO window and by removing PCI_COMMAND_IO from the setup register. Signed-off-by: Fabrice Gasnier Signed-off-by: Gabriel Fernandez --- .../devicetree/bindings/pci/designware-pcie.txt | 2 ++ drivers/pci/host/pcie-designware.c | 24 ++++++++++++++++++++-- drivers/pci/host/pcie-designware.h | 1 + 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index 9f4faa8..40544d4 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -26,3 +26,5 @@ Optional properties: - bus-range: PCI bus numbers covered (it is recommended for new devicetrees to specify this property, to keep backwards compatibility a range of 0x00-0xff is assumed if not present) +- disable_io_support: set this property for PCIe host controller without IO + port access diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 1f4ea6f..f9d70f5 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -471,6 +471,9 @@ int __init dw_pcie_host_init(struct pcie_port *pp) return -EINVAL; } + pp->disable_io_support = of_property_read_bool(np, + "disable_io_support"); + if (IS_ENABLED(CONFIG_PCI_MSI)) { if (!pp->ops->msi_host_init) { pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, @@ -704,6 +707,7 @@ static struct pci_ops dw_pcie_ops = { static int dw_pcie_setup(int nr, struct pci_sys_data *sys) { struct pcie_port *pp; + struct resource *res; pp = sys_to_pcie(sys); @@ -719,6 +723,18 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys) pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); pci_add_resource(&sys->resources, &pp->busn); + if (pp->disable_io_support) { + /* This PCIe controller does not support IO, set an empty one */ + res = devm_kzalloc(pp->dev, sizeof(*res), GFP_KERNEL); + if (res) { + res->start = 0; + res->end = 0; + res->name = "PCIe empty IO space"; + res->flags = IORESOURCE_IO; + pci_add_resource(&sys->resources, res); + } + } + return 1; } @@ -822,8 +838,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) /* setup command register */ dw_pcie_readl_rc(pp, PCI_COMMAND, &val); val &= 0xffff0000; - val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_SERR; + + if (!pp->disable_io_support) + val |= PCI_COMMAND_IO; + + val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; + dw_pcie_writel_rc(pp, val, PCI_COMMAND); } diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index d0bbd27..027045d 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -52,6 +52,7 @@ struct pcie_port { int msi_irq; struct irq_domain *irq_domain; unsigned long msi_data; + bool disable_io_support; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); };