From patchwork Thu Mar 12 21:55:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 449677 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id EDD0B14009B for ; Fri, 13 Mar 2015 08:57:17 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="verification failed; unprotected key" header.d=gmail.com header.i=@gmail.com header.b=ffx/h5y1; dkim-adsp=none (unprotected policy); dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756113AbbCLV5P (ORCPT ); Thu, 12 Mar 2015 17:57:15 -0400 Received: from mail-we0-f169.google.com ([74.125.82.169]:37776 "EHLO mail-we0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756024AbbCLV4w (ORCPT ); Thu, 12 Mar 2015 17:56:52 -0400 Received: by wesx3 with SMTP id x3so19410935wes.4; Thu, 12 Mar 2015 14:56:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YloSVoZc+C24U3xCgbUTOXyF0bDn+n1R3St6ZuN6Mxc=; b=ffx/h5y148tMRAeFcfY1OPpHwQJnOnapW2TxnCawgBxu3hHg0z88lCPTWrCS2Z6h6u HZ0r9x7kBGvAUwd6hBOfV9nTIM5poKPUW4gJMgDa2ULOMRZiK/p/DmdizBPzveOEYCCJ fmnNeNg5nOANjpPtRsuRH2PP8KCi6hkWiKkva65iaT5xbUc+ll8mBZpBZv0wJKq3GYY4 12mjTb6ijhnK2JR3sp8ZDUTIywXroKHTBkZSrS1SBX3662iwbkEVWlRd3lhFFT8q6mqc rjpZQXUZC3UgOS/pgCOsmNrUaTI2q/ZABNwZQMpO9BcOHtsrrPLALN3WXX7o0BMwyIyF QghA== X-Received: by 10.194.121.68 with SMTP id li4mr91680209wjb.138.1426197407168; Thu, 12 Mar 2015 14:56:47 -0700 (PDT) Received: from lmecul0520.st.com. (246.208.139.88.rev.sfr.net. [88.139.208.246]) by mx.google.com with ESMTPSA id hl8sm148976wjb.38.2015.03.12.14.56.44 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Mar 2015 14:56:46 -0700 (PDT) From: Maxime Coquelin X-Google-Original-From: Maxime Coquelin To: u.kleine-koenig@pengutronix.de, afaerber@suse.de, geert@linux-m68k.org, Rob Herring , Philipp Zabel , Linus Walleij , Arnd Bergmann , stefan@agner.ch, pmeerw@pmeerw.net, pebolle@tiscali.nl Cc: Jonathan Corbet , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Daniel Lezcano , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Andrew Morton , "David S. Miller" , Mauro Carvalho Chehab , Joe Perches , Antti Palosaari , Tejun Heo , Will Deacon , Nikolay Borisov , Rusty Russell , Kees Cook , Michal Marek , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, mcoquelin.stm32@gmail.com Subject: [PATCH v3 09/15] dt-bindings: Document the STM32 USART bindings Date: Thu, 12 Mar 2015 22:55:55 +0100 Message-Id: <1426197361-19290-10-git-send-email-maxime.coquelin@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1426197361-19290-1-git-send-email-maxime.coquelin@st.com> References: <1426197361-19290-1-git-send-email-maxime.coquelin@st.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Maxime Coquelin This adds documentation of device tree bindings for the STM32 USART Signed-off-by: Maxime Coquelin --- .../devicetree/bindings/serial/st,stm32-usart.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/st,stm32-usart.txt diff --git a/Documentation/devicetree/bindings/serial/st,stm32-usart.txt b/Documentation/devicetree/bindings/serial/st,stm32-usart.txt new file mode 100644 index 0000000..090a3a4 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/st,stm32-usart.txt @@ -0,0 +1,32 @@ +* STMicroelectronics STM32 USART + +Required properties: +- compatible: Can be either "st,stm32-usart" or "st,stm32-uart" depending on +whether the device supports synchronous mode. +- reg: The address and length of the peripheral registers space +- interrupts: The interrupt line of the USART instance +- clocks: The input clock of the USART instance + +Optional properties: +- pinctrl: The reference on the pins configuration +- st,hw-flow-ctrl: bool flag to enable hardware flow control. + +Examples: +usart4: serial@40004c00 { + compatible = "st,stm32-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52>; + clocks = <&clk_pclk1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart4>; +}; + +usart2: serial@40004400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004400 0x400>; + interrupts = <38>; + clocks = <&clk_pclk1>; + st,hw-flow-ctrl; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rtscts>; +};