From patchwork Thu Mar 12 21:55:51 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 449668 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 25FBC140146 for ; Fri, 13 Mar 2015 08:56:54 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="verification failed; unprotected key" header.d=gmail.com header.i=@gmail.com header.b=vB/aQ+do; dkim-adsp=none (unprotected policy); dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756011AbbCLV4t (ORCPT ); Thu, 12 Mar 2015 17:56:49 -0400 Received: from mail-we0-f169.google.com ([74.125.82.169]:34629 "EHLO mail-we0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755935AbbCLV4g (ORCPT ); Thu, 12 Mar 2015 17:56:36 -0400 Received: by wesx3 with SMTP id x3so19401902wes.1; Thu, 12 Mar 2015 14:56:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tDhAj77OeryxMb0PUIPthdFs0wvOQj03xkYgBK31I+Y=; b=vB/aQ+doja2qJn43J71XrWLMR69bRes1p7Fi56DxG1eQq7qXSum1fReawk61Zqexl2 1xdbqC3UKrJmv0dI5n1QSP3S+qnVWIaSKMYBsk9ZkR6cBL9hKd2bd1QNOXI9A7ma7G+V m/jQn9JhwXoWvfuvjcC2o+RDx2kn+yEn4tXQ9RT7CiE34NAP9QkpNASaztiys57EzItR 4WifO3XjjFny2g4lC/caZsHm1o5W/5rRIXlbqgf9P/JF+kwV2qbJqN+GmBuaJshu14+4 NrAukwwzcMTpu/pvugIUL0pQOUIDX8CPlRF+l/3R7GPh+bRuYbMhR24vCQoo9gdzBDCh Zoxg== X-Received: by 10.194.241.202 with SMTP id wk10mr65315209wjc.145.1426197393984; Thu, 12 Mar 2015 14:56:33 -0700 (PDT) Received: from lmecul0520.st.com. (246.208.139.88.rev.sfr.net. [88.139.208.246]) by mx.google.com with ESMTPSA id hl8sm148976wjb.38.2015.03.12.14.56.31 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Mar 2015 14:56:33 -0700 (PDT) From: Maxime Coquelin X-Google-Original-From: Maxime Coquelin To: u.kleine-koenig@pengutronix.de, afaerber@suse.de, geert@linux-m68k.org, Rob Herring , Philipp Zabel , Linus Walleij , Arnd Bergmann , stefan@agner.ch, pmeerw@pmeerw.net, pebolle@tiscali.nl Cc: Jonathan Corbet , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Daniel Lezcano , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Andrew Morton , "David S. Miller" , Mauro Carvalho Chehab , Joe Perches , Antti Palosaari , Tejun Heo , Will Deacon , Nikolay Borisov , Rusty Russell , Kees Cook , Michal Marek , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, mcoquelin.stm32@gmail.com Subject: [PATCH v3 05/15] dt-bindings: Document the STM32 reset bindings Date: Thu, 12 Mar 2015 22:55:51 +0100 Message-Id: <1426197361-19290-6-git-send-email-maxime.coquelin@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1426197361-19290-1-git-send-email-maxime.coquelin@st.com> References: <1426197361-19290-1-git-send-email-maxime.coquelin@st.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Maxime Coquelin This adds documentation of device tree bindings for the STM32 reset controller. Signed-off-by: Maxime Coquelin --- .../devicetree/bindings/reset/st,stm32-rcc.txt | 102 +++++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/st,stm32-rcc.txt diff --git a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt new file mode 100644 index 0000000..962f961 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt @@ -0,0 +1,102 @@ +STMicroelectronics STM32 Peripheral Reset Controller +==================================================== + +The RCC IP is both a reset and a clock controller. This documentation only +document the reset part. + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "st,stm32-rcc" +- reg: should be register base and length as documented in the + datasheet +- #reset-cells: 1, see below + +example: + +rcc: reset@40023800 { + #reset-cells = <1>; + compatible = "st,stm32-rcc"; + reg = <0x40023800 0x400>; +}; + +Specifying softreset control of devices +======================================= + +Device nodes should specify the reset channel required in their "resets" +property, containing a phandle to the reset device node and an index specifying +which channel to use. + +example: + + timer2 { + resets = <&rcc 256>; + }; + +List of indexes for STM32F429: + - gpioa: 128 + - gpiob: 129 + - gpioc: 130 + - gpiod: 131 + - gpioe: 132 + - gpiof: 133 + - gpiog: 134 + - gpioh: 135 + - gpioi: 136 + - gpioj: 137 + - gpiok: 138 + - crc: 140 + - dma1: 149 + - dma2: 150 + - dma2d: 151 + - ethmac: 153 + - otghs: 157 + - dcmi: 160 + - cryp: 164 + - hash: 165 + - rng: 166 + - otgfs: 167 + - fmc: 192 + - tim2: 256 + - tim3: 257 + - tim4: 258 + - tim5: 259 + - tim6: 260 + - tim7: 261 + - tim12: 262 + - tim13: 263 + - tim14: 264 + - wwdg: 267 + - spi2: 270 + - spi3: 271 + - uart2: 273 + - uart3: 274 + - uart4: 275 + - uart5: 276 + - i2c1: 277 + - i2c2: 278 + - i2c3: 279 + - can1: 281 + - can2: 282 + - pwr: 284 + - dac: 285 + - uart7: 286 + - uart8: 287 + - tim1: 288 + - tim8: 289 + - usart1: 292 + - usart6: 293 + - adc: 296 + - sdio: 299 + - spi1: 300 + - spi4: 301 + - syscfg: 302 + - tim9: 304 + - tim10: 305 + - tim11: 306 + - spi5: 308 + - spi6: 309 + - sai1: 310 + - ltdc: 31 +