| Message ID | 1426044356-15842-1-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | Accepted |
| Delegated to: | Simon Glass |
| Headers | show |
Hi Bin, On 10 March 2015 at 20:25, Bin Meng <bmeng.cn@gmail.com> wrote: > Intel Quark SoC integrates two 10/100 ethernet controllers which can > be connected to an external RMII PHY. The MAC IP is from Designware. > Enable this support with the existing U-Boot Designware MAC driver > so that the ethernet port on Intel Galileo board can be used. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > --- > > arch/x86/cpu/quark/quark.c | 19 +++++++++++++++++++ > include/configs/galileo.h | 5 +++++ > 2 files changed, 24 insertions(+) > > diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c > index dccf7ac..25edcf7 100644 > --- a/arch/x86/cpu/quark/quark.c > +++ b/arch/x86/cpu/quark/quark.c > @@ -6,6 +6,8 @@ > > #include <common.h> > #include <mmc.h> > +#include <netdev.h> > +#include <phy.h> > #include <asm/io.h> > #include <asm/pci.h> > #include <asm/post.h> > @@ -116,3 +118,20 @@ int cpu_mmc_init(bd_t *bis) > return pci_mmc_init("Quark SDHCI", mmc_supported, > ARRAY_SIZE(mmc_supported)); > } > + > +int cpu_eth_init(bd_t *bis) > +{ > + u32 base; > + int ret0, ret1; > + > + pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, &base); > + ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII); > + > + pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, &base); > + ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII); > + > + if (ret0 < 0 && ret1 < 0) > + return -1; > + else > + return 0; > +} > diff --git a/include/configs/galileo.h b/include/configs/galileo.h > index d745f4e..65a2c3e 100644 > --- a/include/configs/galileo.h > +++ b/include/configs/galileo.h > @@ -57,4 +57,9 @@ > #define CONFIG_MMC_SDMA > #define CONFIG_CMD_MMC > > +/* 10/100M Ethernet support */ > +#define CONFIG_DESIGNWARE_ETH > +#define CONFIG_DW_ALTDESCRIPTOR > +#define CONFIG_PHYLIB > + > #endif /* __CONFIG_H */ > -- > 1.8.2.1 > Acked-by: Simon Glass <sjg@chromium.org> BTW I expect the driver model Ethernet support to land soon, and I sent a series that moves the Designware Ethernet to driver model. So by the time we come to apply this, we may want to use that. But as things stand it looks good. Regards, Simon
On 12 March 2015 at 16:13, Simon Glass <sjg@chromium.org> wrote: > Hi Bin, > > On 10 March 2015 at 20:25, Bin Meng <bmeng.cn@gmail.com> wrote: >> Intel Quark SoC integrates two 10/100 ethernet controllers which can >> be connected to an external RMII PHY. The MAC IP is from Designware. >> Enable this support with the existing U-Boot Designware MAC driver >> so that the ethernet port on Intel Galileo board can be used. >> >> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >> --- >> >> arch/x86/cpu/quark/quark.c | 19 +++++++++++++++++++ >> include/configs/galileo.h | 5 +++++ >> 2 files changed, 24 insertions(+) Since this only affects this new board we may as well apply it now. Applied to u-boot-x86, thanks!
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index dccf7ac..25edcf7 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -6,6 +6,8 @@ #include <common.h> #include <mmc.h> +#include <netdev.h> +#include <phy.h> #include <asm/io.h> #include <asm/pci.h> #include <asm/post.h> @@ -116,3 +118,20 @@ int cpu_mmc_init(bd_t *bis) return pci_mmc_init("Quark SDHCI", mmc_supported, ARRAY_SIZE(mmc_supported)); } + +int cpu_eth_init(bd_t *bis) +{ + u32 base; + int ret0, ret1; + + pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, &base); + ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII); + + pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, &base); + ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII); + + if (ret0 < 0 && ret1 < 0) + return -1; + else + return 0; +} diff --git a/include/configs/galileo.h b/include/configs/galileo.h index d745f4e..65a2c3e 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -57,4 +57,9 @@ #define CONFIG_MMC_SDMA #define CONFIG_CMD_MMC +/* 10/100M Ethernet support */ +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_PHYLIB + #endif /* __CONFIG_H */
Intel Quark SoC integrates two 10/100 ethernet controllers which can be connected to an external RMII PHY. The MAC IP is from Designware. Enable this support with the existing U-Boot Designware MAC driver so that the ethernet port on Intel Galileo board can be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- arch/x86/cpu/quark/quark.c | 19 +++++++++++++++++++ include/configs/galileo.h | 5 +++++ 2 files changed, 24 insertions(+)