From patchwork Sat Feb 6 16:40:44 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 44707 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A2A50B7CE2 for ; Sun, 7 Feb 2010 03:47:29 +1100 (EST) Received: from localhost ([127.0.0.1]:38305 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ndnm2-0006ii-Pd for incoming@patchwork.ozlabs.org; Sat, 06 Feb 2010 11:44:46 -0500 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Ndnji-0006TC-O4 for qemu-devel@nongnu.org; Sat, 06 Feb 2010 11:42:22 -0500 Received: from [199.232.76.173] (port=59287 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ndnji-0006T4-9f for qemu-devel@nongnu.org; Sat, 06 Feb 2010 11:42:22 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1Ndnjg-0004EE-7K for qemu-devel@nongnu.org; Sat, 06 Feb 2010 11:42:22 -0500 Received: from mx20.gnu.org ([199.232.41.8]:39458) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Ndnjd-0003kf-OE for qemu-devel@nongnu.org; Sat, 06 Feb 2010 11:42:20 -0500 Received: from hall.aurel32.net ([88.191.82.174]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NdniK-0005gu-Ps for qemu-devel@nongnu.org; Sat, 06 Feb 2010 11:40:57 -0500 Received: from [2002:52e8:2fb:1:21e:8cff:feb0:693b] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1NdniB-0007na-3a; Sat, 06 Feb 2010 17:40:47 +0100 Received: from aurel32 by volta.aurel32.net with local (Exim 4.71) (envelope-from ) id 1NdniA-0005zO-Dt; Sat, 06 Feb 2010 17:40:46 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 6 Feb 2010 17:40:44 +0100 Message-Id: <1265474444-22991-1-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.6.6.1 X-detected-operating-system: by mx20.gnu.org: GNU/Linux 2.6 (newer, 3) X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH] target-sh4: minor optimisations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Aurelien Jarno --- target-sh4/translate.c | 52 ++++++++++++++++++++++++------------------------ 1 files changed, 26 insertions(+), 26 deletions(-) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 895b978..8f0a986 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -664,7 +664,7 @@ static void _decode_opc(DisasContext * ctx) TCGv addr = tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 1); tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */ - tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); /* modify register status */ + tcg_gen_mov_i32(REG(B11_8), addr); /* modify register status */ tcg_temp_free(addr); } return; @@ -673,7 +673,7 @@ static void _decode_opc(DisasContext * ctx) TCGv addr = tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 2); tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); - tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2); + tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); } return; @@ -682,7 +682,7 @@ static void _decode_opc(DisasContext * ctx) TCGv addr = tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 4); tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); - tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); + tcg_gen_mov_i32(REG(B11_8), addr); } return; case 0x6004: /* mov.b @Rm+,Rn */ @@ -750,17 +750,13 @@ static void _decode_opc(DisasContext * ctx) return; case 0x6008: /* swap.b Rm,Rn */ { - TCGv highw, high, low; - highw = tcg_temp_new(); - tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000); + TCGv high, low; high = tcg_temp_new(); - tcg_gen_ext8u_i32(high, REG(B7_4)); - tcg_gen_shli_i32(high, high, 8); + tcg_gen_andi_i32(high, REG(B7_4), 0xffff0000); low = tcg_temp_new(); - tcg_gen_shri_i32(low, REG(B7_4), 8); - tcg_gen_ext8u_i32(low, low); + tcg_gen_ext16u_i32(low, REG(B7_4)); + tcg_gen_bswap16_i32(low, low); tcg_gen_or_i32(REG(B11_8), high, low); - tcg_gen_or_i32(REG(B11_8), REG(B11_8), highw); tcg_temp_free(low); tcg_temp_free(high); } @@ -769,8 +765,7 @@ static void _decode_opc(DisasContext * ctx) { TCGv high, low; high = tcg_temp_new(); - tcg_gen_ext16u_i32(high, REG(B7_4)); - tcg_gen_shli_i32(high, high, 16); + tcg_gen_shli_i32(high, REG(B7_4), 16); low = tcg_temp_new(); tcg_gen_shri_i32(low, REG(B7_4), 16); tcg_gen_ext16u_i32(low, low); @@ -783,8 +778,7 @@ static void _decode_opc(DisasContext * ctx) { TCGv high, low; high = tcg_temp_new(); - tcg_gen_ext16u_i32(high, REG(B7_4)); - tcg_gen_shli_i32(high, high, 16); + tcg_gen_shli_i32(high, REG(B7_4), 16); low = tcg_temp_new(); tcg_gen_shri_i32(low, REG(B11_8), 16); tcg_gen_ext16u_i32(low, low); @@ -974,20 +968,24 @@ static void _decode_opc(DisasContext * ctx) int label2 = gen_new_label(); int label3 = gen_new_label(); int label4 = gen_new_label(); - TCGv shift = tcg_temp_local_new(); + TCGv shift; tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1); /* Rm positive, shift to the left */ + shift = tcg_temp_new(); tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); + tcg_temp_free(shift); tcg_gen_br(label4); /* Rm negative, shift to the right */ gen_set_label(label1); + shift = tcg_temp_new(); tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2); tcg_gen_not_i32(shift, REG(B7_4)); tcg_gen_andi_i32(shift, shift, 0x1f); tcg_gen_addi_i32(shift, shift, 1); tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift); + tcg_temp_free(shift); tcg_gen_br(label4); /* Rm = -32 */ gen_set_label(label2); @@ -997,7 +995,6 @@ static void _decode_opc(DisasContext * ctx) gen_set_label(label3); tcg_gen_movi_i32(REG(B11_8), 0xffffffff); gen_set_label(label4); - tcg_temp_free(shift); } return; case 0x400d: /* shld Rm,Rn */ @@ -1005,26 +1002,29 @@ static void _decode_opc(DisasContext * ctx) int label1 = gen_new_label(); int label2 = gen_new_label(); int label3 = gen_new_label(); - TCGv shift = tcg_temp_local_new(); + TCGv shift; tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1); /* Rm positive, shift to the left */ + shift = tcg_temp_new(); tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); + tcg_temp_free(shift); tcg_gen_br(label3); /* Rm negative, shift to the right */ gen_set_label(label1); + shift = tcg_temp_new(); tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2); tcg_gen_not_i32(shift, REG(B7_4)); tcg_gen_andi_i32(shift, shift, 0x1f); tcg_gen_addi_i32(shift, shift, 1); tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift); + tcg_temp_free(shift); tcg_gen_br(label3); /* Rm = -32 */ gen_set_label(label2); tcg_gen_movi_i32(REG(B11_8), 0); gen_set_label(label3); - tcg_temp_free(shift); } return; case 0x3008: /* sub Rm,Rn */ @@ -1106,7 +1106,7 @@ static void _decode_opc(DisasContext * ctx) int fr = XREG(B7_4); tcg_gen_subi_i32(addr, REG(B11_8), 4); tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx); - tcg_gen_subi_i32(addr, REG(B11_8), 8); + tcg_gen_subi_i32(addr, addr, 4); tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx); tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); @@ -1115,8 +1115,8 @@ static void _decode_opc(DisasContext * ctx) addr = tcg_temp_new_i32(); tcg_gen_subi_i32(addr, REG(B11_8), 4); tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx); + tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); - tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); } return; case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ @@ -1436,8 +1436,8 @@ static void _decode_opc(DisasContext * ctx) TCGv addr = tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 4); tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx); + tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); - tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); } return; } @@ -1505,8 +1505,8 @@ static void _decode_opc(DisasContext * ctx) TCGv addr = tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 4); tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx); + tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); - tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); } return; #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \ @@ -1526,11 +1526,11 @@ static void _decode_opc(DisasContext * ctx) case stpnum: \ prechk \ { \ - TCGv addr = tcg_temp_new(); \ + TCGv addr = tcg_temp_new(); \ tcg_gen_subi_i32(addr, REG(B11_8), 4); \ tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \ + tcg_gen_mov_i32(REG(B11_8), addr); \ tcg_temp_free(addr); \ - tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); \ } \ return; LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {}) @@ -1571,9 +1571,9 @@ static void _decode_opc(DisasContext * ctx) addr = tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 4); tcg_gen_qemu_st32(val, addr, ctx->memidx); + tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); tcg_temp_free(val); - tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); } return; case 0x00c3: /* movca.l R0,@Rm */