| Message ID | 1425391409-25576-2-git-send-email-ajaykumar.rs@samsung.com |
|---|---|
| State | Superseded |
| Headers | show |
Hi Ajay, On 3 March 2015 at 07:03, Ajay Kumar <ajaykumar.rs@samsung.com> wrote: > Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by > exynos video driver. > > Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> > --- > arch/arm/cpu/armv7/exynos/clock.c | 66 ++++++++++++++++++++++++++++++-- > arch/arm/include/asm/arch-exynos/clk.h | 3 ++ > 2 files changed, 66 insertions(+), 3 deletions(-) Reviewed-by: Simon Glass <sjg@chromium.org> (one question below) Tested on Pi. Tested-by: Simon Glass <sjg@chromium.org> > > diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c > index c6455c2..23f8ff7 100644 > --- a/arch/arm/cpu/armv7/exynos/clock.c > +++ b/arch/arm/cpu/armv7/exynos/clock.c > @@ -14,7 +14,7 @@ > #define PLL_DIV_1024 1024 > #define PLL_DIV_65535 65535 > #define PLL_DIV_65536 65536 > - > +#define FIN_HZ 24000000 Is this different from CONFIG_SYS_CLK_FREQ? > /* * > * This structure is to store the src bit, div bit and prediv bit > * positions of the peripheral clocks of the src and div registers > @@ -1028,6 +1028,40 @@ static unsigned long exynos5420_get_lcd_clk(void) > return pclk; > } > > +static unsigned long exynos5800_get_lcd_clk(void) > +{ > + struct exynos5420_clock *clk = > + (struct exynos5420_clock *)samsung_get_base_clock(); > + unsigned long sclk; > + unsigned int sel; > + unsigned int ratio; > + > + /* > + * CLK_SRC_DISP10 > + * CLKMUX_FIMD1 [6:4] > + */ > + sel = (readl(&clk->src_disp10) >> 4) & 0x7; > + > + if (sel) { > + /* > + * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into > + * PLLs. The first element is a placeholder to bypass the > + * default settig. > + */ > + const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, > + RPLL}; > + sclk = get_pll_clk(reg_map[sel]); > + } else > + sclk = FIN_HZ; > + /* > + * CLK_DIV_DISP10 > + * FIMD1_RATIO [3:0] > + */ > + ratio = readl(&clk->div_disp10) & 0xf; > + > + return sclk / (ratio + 1); > +} > + > void exynos4_set_lcd_clk(void) > { > struct exynos4_clock *clk = > @@ -1159,6 +1193,28 @@ void exynos5420_set_lcd_clk(void) > writel(cfg, &clk->div_disp10); > } > > +void exynos5800_set_lcd_clk(void) > +{ > + struct exynos5420_clock *clk = > + (struct exynos5420_clock *)samsung_get_base_clock(); > + unsigned int cfg; > + > + /* > + * Use RPLL for pixel clock > + * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] > + * ================== > + * 111: SCLK_RPLL > + */ > + cfg = readl(&clk->src_disp10) | (0x7 << 4); > + writel(cfg, &clk->src_disp10); > + > + /* > + * CLK_DIV_DISP10 > + * FIMD1_RATIO [3:0] > + */ > + clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0); > +} > + > void exynos4_set_mipi_clk(void) > { > struct exynos4_clock *clk = > @@ -1646,8 +1702,10 @@ unsigned long get_lcd_clk(void) > if (cpu_is_exynos4()) > return exynos4_get_lcd_clk(); > else { > - if (proid_is_exynos5420() || proid_is_exynos5800()) > + if (proid_is_exynos5420()) > return exynos5420_get_lcd_clk(); > + else if (proid_is_exynos5800()) > + return exynos5800_get_lcd_clk(); > else > return exynos5_get_lcd_clk(); > } > @@ -1660,8 +1718,10 @@ void set_lcd_clk(void) > else { > if (proid_is_exynos5250()) > exynos5_set_lcd_clk(); > - else if (proid_is_exynos5420() || proid_is_exynos5800()) > + else if (proid_is_exynos5420()) > exynos5420_set_lcd_clk(); > + else > + exynos5800_set_lcd_clk(); > } > } > > diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h > index 2a17dfc..d20b7d2 100644 > --- a/arch/arm/include/asm/arch-exynos/clk.h > +++ b/arch/arm/include/asm/arch-exynos/clk.h > @@ -16,6 +16,9 @@ > #define BPLL 5 > #define RPLL 6 > #define SPLL 7 > +#define CPLL 8 > +#define DPLL 9 > +#define IPLL 10 > > #define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8)) > #define MASK_RATIO(x) (0xf << (x << 4)) > -- > 1.7.9.5 > Regards, Simon
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index c6455c2..23f8ff7 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -14,7 +14,7 @@ #define PLL_DIV_1024 1024 #define PLL_DIV_65535 65535 #define PLL_DIV_65536 65536 - +#define FIN_HZ 24000000 /* * * This structure is to store the src bit, div bit and prediv bit * positions of the peripheral clocks of the src and div registers @@ -1028,6 +1028,40 @@ static unsigned long exynos5420_get_lcd_clk(void) return pclk; } +static unsigned long exynos5800_get_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_DISP10 + * CLKMUX_FIMD1 [6:4] + */ + sel = (readl(&clk->src_disp10) >> 4) & 0x7; + + if (sel) { + /* + * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into + * PLLs. The first element is a placeholder to bypass the + * default settig. + */ + const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, + RPLL}; + sclk = get_pll_clk(reg_map[sel]); + } else + sclk = FIN_HZ; + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + ratio = readl(&clk->div_disp10) & 0xf; + + return sclk / (ratio + 1); +} + void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1159,6 +1193,28 @@ void exynos5420_set_lcd_clk(void) writel(cfg, &clk->div_disp10); } +void exynos5800_set_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned int cfg; + + /* + * Use RPLL for pixel clock + * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] + * ================== + * 111: SCLK_RPLL + */ + cfg = readl(&clk->src_disp10) | (0x7 << 4); + writel(cfg, &clk->src_disp10); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0); +} + void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -1646,8 +1702,10 @@ unsigned long get_lcd_clk(void) if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); else { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420()) return exynos5420_get_lcd_clk(); + else if (proid_is_exynos5800()) + return exynos5800_get_lcd_clk(); else return exynos5_get_lcd_clk(); } @@ -1660,8 +1718,10 @@ void set_lcd_clk(void) else { if (proid_is_exynos5250()) exynos5_set_lcd_clk(); - else if (proid_is_exynos5420() || proid_is_exynos5800()) + else if (proid_is_exynos5420()) exynos5420_set_lcd_clk(); + else + exynos5800_set_lcd_clk(); } } diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 2a17dfc..d20b7d2 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -16,6 +16,9 @@ #define BPLL 5 #define RPLL 6 #define SPLL 7 +#define CPLL 8 +#define DPLL 9 +#define IPLL 10 #define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8)) #define MASK_RATIO(x) (0xf << (x << 4))
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by exynos video driver. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> --- arch/arm/cpu/armv7/exynos/clock.c | 66 ++++++++++++++++++++++++++++++-- arch/arm/include/asm/arch-exynos/clk.h | 3 ++ 2 files changed, 66 insertions(+), 3 deletions(-)