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[U-Boot,V2,5/9] ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870

Message ID 1424818672-29501-6-git-send-email-nm@ti.com
State Superseded
Delegated to: Tom Rini
Headers show

Commit Message

Nishanth Menon Feb. 24, 2015, 10:57 p.m. UTC 
From: Praveen Rao <prao@ti.com>

This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

An implementation for OMAP5 and DRA7 is introduced here as well.
Obviously, implementations for other SoC families such as Exynos etc
will be widely different.

Signed-off-by: Praveen Rao <prao@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 README                                      |    1 +
 arch/arm/cpu/armv7/omap5/Makefile           |    1 +
 arch/arm/cpu/armv7/omap5/lowlevel_init.S    |   46 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap5/sys_proto.h |    1 +
 4 files changed, 49 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/omap5/lowlevel_init.S
diff mbox

Patch

diff --git a/README b/README
index 2e53e0c5757d..d76cdc68d406 100644
--- a/README
+++ b/README
@@ -625,6 +625,7 @@  The following options need to be configured:
 		with CONFIG_ARM_ARCH_CP15_ERRATA define. These need to have an
 		SoC specific implementation of the erratum workaround to
 		function.
+		CONFIG_ARM_ERRATA_798870
 
 - Driver Model
 		Driver model is a new framework for devices in U-Boot
diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile
index 64c68791f18e..b645dd4f58b7 100644
--- a/arch/arm/cpu/armv7/omap5/Makefile
+++ b/arch/arm/cpu/armv7/omap5/Makefile
@@ -11,3 +11,4 @@  obj-y	+= sdram.o
 obj-y	+= prcm-regs.o
 obj-y	+= hw_data.o
 obj-y	+= abb.o
+obj-y	+= lowlevel_init.o
diff --git a/arch/arm/cpu/armv7/omap5/lowlevel_init.S b/arch/arm/cpu/armv7/omap5/lowlevel_init.S
new file mode 100644
index 000000000000..974e3a59fb08
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap5/lowlevel_init.S
@@ -0,0 +1,46 @@ 
+/*
+ * Board specific misc setup
+ *
+ * (C) Copyright 2015
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
+#include <asm/arch/spl.h>
+#include <linux/linkage.h>
+
+#define OMAP5_SERVICE_L2ACTLR_SET    0x104
+
+#ifdef CONFIG_ARM_ARCH_CP15_ERRATA
+	.globl	arch_cp15_errata_workaround
+/*
+ * R0 has MIDR
+ * R1 has CPU Variant (bits 20-23)
+ * R2 has CPU Revision (bits 0-3)
+ * R3 is compbined CPU variant << 4 + CPU revision
+ */
+ENTRY(arch_cp15_errata_workaround)
+	push	{r4-r11, lr}	@ save registers - ROM code may pollute
+
+#ifdef CONFIG_ARM_ERRATA_798870
+	/* We are r2p2, but anyways for completeness.. */
+	cmp	r3, #0x30		@ Applies to lower than R3p0
+	bge     skip_errata_798870      @ skip if not affected rev
+	cmp	r3, #0x20		@ Applies to including and above R2p0
+	blt     skip_errata_798870      @ skip if not affected rev
+
+	mrc     p15, 1, r1, c15, c0, 0  @ read l2 aux ctrl reg
+	orr     r1, r1, #1 << 7         @ set bit #7
+	ldr     r0, =OMAP5_SERVICE_L2ACTLR_SET    @ Set L2 Cache Auxiliary control register - value in R0
+	b omap_smc1
+
+skip_errata_798870:
+#endif
+	pop	{r4-r11, pc}
+ENDPROC(arch_cp15_errata_workaround)
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 103830319a41..0a7a52d138df 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -56,6 +56,7 @@  void force_emif_self_refresh(void);
 void get_ioregs(const struct ctrl_ioregs **regs);
 void srcomp_enable(void);
 void setup_warmreset_time(void);
+void omap_smc1(u32 service, u32 val);
 
 static inline u32 div_round_up(u32 num, u32 den)
 {