From patchwork Tue Feb 24 21:52:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: DJ Delorie X-Patchwork-Id: 443195 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E1E2614009B for ; Wed, 25 Feb 2015 08:52:36 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject; q=dns; s=default; b=QWIwukpe1uqrjve pUPYeORtyou96fjyHS+CLGnhy2TE33JuxBXXkgnpFidUPxnalb3wzAYrVb+OOw/+ 1JSH3P1I6Wu1uCpm+WfoZ3rfhvcIHNaRrUVw3T1dctvFhpKMLHrFimt2gdSHJiK7 HYBrLcKW0pbiEIFcOaI47qjclG4w= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject; s=default; bh=JZ4ZmNA7EgbxEANG8++6B r8TNZo=; b=xq0cUPdHXaeueor6YM4WEUb2h5LAJnh9KfQ66Oj8pk7pK7CRXzTOD BC7YFrjOo3WQPArbo9CKCLe59pXukbxZu9YKezcKTMGX7voNDCuRkddUDAP2pTJU geA7DYZUW3xBxAn07uMfwoAMMopRsO/HdZFdNHDz3UfkHWcZlMHCcU= Received: (qmail 59133 invoked by alias); 24 Feb 2015 21:52:28 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59122 invoked by uid 89); 24 Feb 2015 21:52:27 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.4 required=5.0 tests=AWL, BAYES_00, SPF_HELO_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Tue, 24 Feb 2015 21:52:25 +0000 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id t1OLqOe8011415 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Tue, 24 Feb 2015 16:52:24 -0500 Received: from greed.delorie.com (ovpn-113-54.phx2.redhat.com [10.3.113.54]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id t1OLqNCx031287 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO) for ; Tue, 24 Feb 2015 16:52:24 -0500 Received: from greed.delorie.com (greed.delorie.com [127.0.0.1]) by greed.delorie.com (8.14.4/8.14.4) with ESMTP id t1OLqNaf005885 for ; Tue, 24 Feb 2015 16:52:23 -0500 Received: (from dj@localhost) by greed.delorie.com (8.14.4/8.14.4/Submit) id t1OLqNTU005883; Tue, 24 Feb 2015 16:52:23 -0500 Date: Tue, 24 Feb 2015 16:52:23 -0500 Message-Id: <201502242152.t1OLqNTU005883@greed.delorie.com> From: DJ Delorie To: gcc-patches@gcc.gnu.org Subject: [rl78] fix SFmode moves X-IsSubscribed: yes SFmode moves were using 8-bit transfers instead of 16-bit. This patch copies the SImode move pattern, which expands into 16-bit moves. Since this only affects rl78, and the SImode code is well tested, I'm applying this now so it will be in gcc 5. * config/rl78/rl78-protos.h (rl78_split_movsi): Accept a mode as well. * config/rl78/rl78-expand.md (movsf): New, same as movsi. * config/rl78/rl78.c (rl78_split_movsi): Accept a mode, use it instead of hardcoding SImode. Index: gcc/config/rl78/rl78-protos.h =================================================================== --- gcc/config/rl78/rl78-protos.h (revision 220948) +++ gcc/config/rl78/rl78-protos.h (working copy) @@ -18,13 +18,13 @@ along with GCC; see the file COPYING3. If not see . */ void rl78_emit_eh_epilogue (rtx); void rl78_expand_compare (rtx *); void rl78_expand_movsi (rtx *); -void rl78_split_movsi (rtx *); +void rl78_split_movsi (rtx *, enum machine_mode); int rl78_force_nonfar_2 (rtx *, rtx (*gen)(rtx,rtx)); int rl78_force_nonfar_3 (rtx *, rtx (*gen)(rtx,rtx,rtx)); void rl78_expand_eh_epilogue (rtx); void rl78_expand_epilogue (void); void rl78_expand_prologue (void); int rl78_far_p (rtx x); Index: gcc/config/rl78/rl78-expand.md =================================================================== --- gcc/config/rl78/rl78-expand.md (revision 220948) +++ gcc/config/rl78/rl78-expand.md (working copy) @@ -84,13 +84,27 @@ "#" "" [(set (match_operand:HI 2 "nonimmediate_operand") (match_operand:HI 4 "general_operand")) (set (match_operand:HI 3 "nonimmediate_operand") (match_operand:HI 5 "general_operand"))] - "rl78_split_movsi (operands);" + "rl78_split_movsi (operands, SImode);" + [(set_attr "valloc" "op1")] +) + +(define_insn_and_split "movsf" + [(set (match_operand:SF 0 "nonimmediate_operand" "=vYS,v,Wfr") + (match_operand:SF 1 "general_operand" "viYS,Wfr,v"))] + "" + "#" + "" + [(set (match_operand:HI 2 "nonimmediate_operand") + (match_operand:HI 4 "general_operand")) + (set (match_operand:HI 3 "nonimmediate_operand") + (match_operand:HI 5 "general_operand"))] + "rl78_split_movsi (operands, SFmode);" [(set_attr "valloc" "op1")] ) ;;---------- Conversions ------------------------ (define_expand "zero_extendqihi2" Index: gcc/config/rl78/rl78.c =================================================================== --- gcc/config/rl78/rl78.c (revision 220948) +++ gcc/config/rl78/rl78.c (working copy) @@ -503,31 +503,31 @@ rl78_expand_movsi (rtx *operands) emit_move_insn (op02, op12); } } /* Generate code to move an SImode value. */ void -rl78_split_movsi (rtx *operands) +rl78_split_movsi (rtx *operands, enum machine_mode omode) { rtx op00, op02, op10, op12; - op00 = rl78_subreg (HImode, operands[0], SImode, 0); - op02 = rl78_subreg (HImode, operands[0], SImode, 2); + op00 = rl78_subreg (HImode, operands[0], omode, 0); + op02 = rl78_subreg (HImode, operands[0], omode, 2); if (GET_CODE (operands[1]) == CONST || GET_CODE (operands[1]) == SYMBOL_REF) { op10 = gen_rtx_ZERO_EXTRACT (HImode, operands[1], GEN_INT (16), GEN_INT (0)); op10 = gen_rtx_CONST (HImode, op10); op12 = gen_rtx_ZERO_EXTRACT (HImode, operands[1], GEN_INT (16), GEN_INT (16)); op12 = gen_rtx_CONST (HImode, op12); } else { - op10 = rl78_subreg (HImode, operands[1], SImode, 0); - op12 = rl78_subreg (HImode, operands[1], SImode, 2); + op10 = rl78_subreg (HImode, operands[1], omode, 0); + op12 = rl78_subreg (HImode, operands[1], omode, 2); } if (rtx_equal_p (operands[0], operands[1])) ; else if (rtx_equal_p (op00, op12)) {