ARM64: Add new Xilinx ZynqMP SoC
diff mbox

Message ID 8ac3037c175711dec0adcd0d898be7d9722e0ed0.1424764548.git.michal.simek@xilinx.com
State New
Headers show

Commit Message

Michal Simek Feb. 24, 2015, 7:56 a.m. UTC
Initial version of device tree for Xilinx ZynqMP SoC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
---

 arch/arm64/Kconfig                          |   5 +
 arch/arm64/boot/dts/Makefile                |   1 +
 arch/arm64/boot/dts/xilinx/Makefile         |   5 +
 arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts |  46 +++++
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi      | 301 ++++++++++++++++++++++++++++
 arch/arm64/configs/defconfig                |   1 +
 6 files changed, 359 insertions(+)
 create mode 100644 arch/arm64/boot/dts/xilinx/Makefile
 create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
 create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp.dtsi

Comments

Rob Herring Feb. 24, 2015, 2:42 p.m. UTC | #1
On Tue, Feb 24, 2015 at 1:56 AM, Michal Simek <michal.simek@xilinx.com> wrote:
> Initial version of device tree for Xilinx ZynqMP SoC.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
> ---

[...]

> +               gic: interrupt-controller@f9010000 {
> +                       compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";

gic-400, right?

> +                       #interrupt-cells = <3>;
> +                       reg = <0x0 0xf9010000 0x10000>,
> +                             <0x0 0xf9020000 0x20000>,
> +                             <0x0 0xf9040000 0x20000>,
> +                             <0x0 0xf9060000 0x20000>;

These addresses are wrong if you are doing address swizzling to do 64K
offsets. We don't really have an answer yet as to what is the right
way. See the XGene GIC discussion[1].

Rob

[1] https://www.mail-archive.com/devicetree@vger.kernel.org/msg62547.html
Michal Simek Feb. 24, 2015, 2:58 p.m. UTC | #2
On 02/24/2015 03:42 PM, Rob Herring wrote:
> On Tue, Feb 24, 2015 at 1:56 AM, Michal Simek <michal.simek@xilinx.com> wrote:
>> Initial version of device tree for Xilinx ZynqMP SoC.
>>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
>> ---
> 
> [...]
> 
>> +               gic: interrupt-controller@f9010000 {
>> +                       compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
> 
> gic-400, right?

yep

> 
>> +                       #interrupt-cells = <3>;
>> +                       reg = <0x0 0xf9010000 0x10000>,
>> +                             <0x0 0xf9020000 0x20000>,
>> +                             <0x0 0xf9040000 0x20000>,
>> +                             <0x0 0xf9060000 0x20000>;
> 
> These addresses are wrong if you are doing address swizzling to do 64K
> offsets. We don't really have an answer yet as to what is the right
> way. See the XGene GIC discussion[1].

Is this better for GICC?
<0x0 0xf902f000 0x2000>

Thanks,
Michal
Rob Herring Feb. 24, 2015, 4:29 p.m. UTC | #3
On Tue, Feb 24, 2015 at 8:58 AM, Michal Simek <michal.simek@xilinx.com> wrote:
> On 02/24/2015 03:42 PM, Rob Herring wrote:
>> On Tue, Feb 24, 2015 at 1:56 AM, Michal Simek <michal.simek@xilinx.com> wrote:
>>> Initial version of device tree for Xilinx ZynqMP SoC.
>>>
>>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>>> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
>>> ---
>>
>> [...]
>>
>>> +               gic: interrupt-controller@f9010000 {
>>> +                       compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
>>
>> gic-400, right?
>
> yep
>
>>
>>> +                       #interrupt-cells = <3>;
>>> +                       reg = <0x0 0xf9010000 0x10000>,
>>> +                             <0x0 0xf9020000 0x20000>,
>>> +                             <0x0 0xf9040000 0x20000>,
>>> +                             <0x0 0xf9060000 0x20000>;
>>
>> These addresses are wrong if you are doing address swizzling to do 64K
>> offsets. We don't really have an answer yet as to what is the right
>> way. See the XGene GIC discussion[1].
>
> Is this better for GICC?
> <0x0 0xf902f000 0x2000>

Yes, and the VCPU interface needs this as well. As far as sizes, we're
still discussing that.

Rob
Michal Simek Feb. 24, 2015, 5:58 p.m. UTC | #4
On 02/24/2015 05:29 PM, Rob Herring wrote:
> On Tue, Feb 24, 2015 at 8:58 AM, Michal Simek <michal.simek@xilinx.com> wrote:
>> On 02/24/2015 03:42 PM, Rob Herring wrote:
>>> On Tue, Feb 24, 2015 at 1:56 AM, Michal Simek <michal.simek@xilinx.com> wrote:
>>>> Initial version of device tree for Xilinx ZynqMP SoC.
>>>>
>>>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>>>> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
>>>> ---
>>>
>>> [...]
>>>
>>>> +               gic: interrupt-controller@f9010000 {
>>>> +                       compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
>>>
>>> gic-400, right?
>>
>> yep
>>
>>>
>>>> +                       #interrupt-cells = <3>;
>>>> +                       reg = <0x0 0xf9010000 0x10000>,
>>>> +                             <0x0 0xf9020000 0x20000>,
>>>> +                             <0x0 0xf9040000 0x20000>,
>>>> +                             <0x0 0xf9060000 0x20000>;
>>>
>>> These addresses are wrong if you are doing address swizzling to do 64K
>>> offsets. We don't really have an answer yet as to what is the right
>>> way. See the XGene GIC discussion[1].
>>
>> Is this better for GICC?
>> <0x0 0xf902f000 0x2000>
> 
> Yes, and the VCPU interface needs this as well. As far as sizes, we're
> still discussing that.

ok. Will test and fix. What about the rest of DT description?

Thanks,
Michal
Mark Rutland Feb. 24, 2015, 6:38 p.m. UTC | #5
Hi Michal,

I have a few minor comments below, but generally this is looking like
one of the best dts submissions I've seen!

[...]

> +/ {
> +       model = "ZynqMP EP108";
> +
> +       aliases {
> +               serial0 = &uart0;
> +       };
> +
> +       chosen {
> +               stdout-path = "serial0:115200n8";
> +       };

Thanks for using stdout-path with the full parameters.

Does your UART have earlycon support?

[...]

> +/ {
> +       compatible = "xlnx,zynqmp";
> +       #address-cells = <2>;
> +       #size-cells = <1>;

I guess this is fine, though to me it feels more natural to use
#size-cells = <2> in case we need to describe larger ranges for some bus
later.

> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               cpu@0 {
> +                       compatible = "arm,cortex-a53", "arm,armv8";
> +                       device_type = "cpu";
> +                       enable-method = "psci";
> +                       reg = <0x0>;
> +               };
> +
> +               cpu@1 {
> +                       compatible = "arm,cortex-a53", "arm,armv8";
> +                       device_type = "cpu";
> +                       enable-method = "psci";
> +                       reg = <0x1>;
> +               };
> +
> +               cpu@2 {
> +                       compatible = "arm,cortex-a53", "arm,armv8";
> +                       device_type = "cpu";
> +                       enable-method = "psci";
> +                       reg = <0x2>;
> +               };
> +
> +               cpu@3 {
> +                       compatible = "arm,cortex-a53", "arm,armv8";
> +                       device_type = "cpu";
> +                       enable-method = "psci";
> +                       reg = <0x3>;
> +               };
> +       };

These look fine.

> +
> +       psci {
> +               compatible = "arm,psci-0.2";
> +               method = "smc";
> +       };

Neat!

What are you using as your implementation? Are all the mandatory
PSCIv0.2 features implemented (e.g. MIGRATE_INFO_TYPE)?

I take it this boots at EL2 on all CPUs?

Does CPU0 hotplug work?

Do you need to keep a CPU online or do you require MIGRATE? e.g. does
MIGRATE_INFO_TYPE return something other than 2 ("MP or not present")?

[...]

> +       amba_apu {
> +               compatible = "simple-bus";
> +               #address-cells = <2>;
> +               #size-cells = <1>;
> +               ranges;
> +
> +               timer {
> +                       compatible = "arm,armv8-timer";
> +                       interrupt-parent = <&gic>;
> +                       interrupts = <1 13 0xff01>,
> +                                    <1 14 0xff01>,
> +                                    <1 11 0xff01>,
> +                                    <1 10 0xff01>;
> +               };

The architected timer should just be under the root node, given it's a
component of the CPU -- it doesn't live on any bus.

I take it CNTFRQ is configured appropriately on all CPUs?

[...]

> +               i2c_clk: i2c_clk {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0x0>;
> +                       clock-frequency = <111111111>;
> +               };

That clock-frequency looks a little odd. Is that right?

I haven't taken an in-depth look at the other nodes. They look sane at a
high-level, and assuming they are all already documented and supported
they look fine to me.

Thanks,
Mark.
Michal Simek Feb. 25, 2015, 2:21 p.m. UTC | #6
Hi Mark,

On 02/24/2015 07:38 PM, Mark Rutland wrote:
> Hi Michal,
> 
> I have a few minor comments below, but generally this is looking like
> one of the best dts submissions I've seen!

thanks appreciate it.

> 
> [...]
> 
>> +/ {
>> +       model = "ZynqMP EP108";
>> +
>> +       aliases {
>> +               serial0 = &uart0;
>> +       };
>> +
>> +       chosen {
>> +               stdout-path = "serial0:115200n8";
>> +       };
> 
> Thanks for using stdout-path with the full parameters.
> 
> Does your UART have earlycon support?

yes earlycon support is already in the kernel.

btw: I found that only stdout-path has different behavior
compare to console=ttyPS0,115200 passed via bootargs.
But I have to look at details to be accurate.


>> +/ {
>> +       compatible = "xlnx,zynqmp";
>> +       #address-cells = <2>;
>> +       #size-cells = <1>;
> 
> I guess this is fine, though to me it feels more natural to use
> #size-cells = <2> in case we need to describe larger ranges for some bus
> later.

I can fix it when it is needed.

> 
>> +       cpus {
>> +               #address-cells = <1>;
>> +               #size-cells = <0>;
>> +
>> +               cpu@0 {
>> +                       compatible = "arm,cortex-a53", "arm,armv8";
>> +                       device_type = "cpu";
>> +                       enable-method = "psci";
>> +                       reg = <0x0>;
>> +               };
>> +
>> +               cpu@1 {
>> +                       compatible = "arm,cortex-a53", "arm,armv8";
>> +                       device_type = "cpu";
>> +                       enable-method = "psci";
>> +                       reg = <0x1>;
>> +               };
>> +
>> +               cpu@2 {
>> +                       compatible = "arm,cortex-a53", "arm,armv8";
>> +                       device_type = "cpu";
>> +                       enable-method = "psci";
>> +                       reg = <0x2>;
>> +               };
>> +
>> +               cpu@3 {
>> +                       compatible = "arm,cortex-a53", "arm,armv8";
>> +                       device_type = "cpu";
>> +                       enable-method = "psci";
>> +                       reg = <0x3>;
>> +               };
>> +       };
> 
> These look fine.

good


>> +
>> +       psci {
>> +               compatible = "arm,psci-0.2";
>> +               method = "smc";
>> +       };
> 
> Neat!
> 
> What are you using as your implementation? Are all the mandatory
> PSCIv0.2 features implemented (e.g. MIGRATE_INFO_TYPE)?

ATF.

> 
> I take it this boots at EL2 on all CPUs?

yep.

> 
> Does CPU0 hotplug work?

cpu shutdown is working fine with the current firmware.
I didn't try anything else.

> 
> Do you need to keep a CPU online or do you require MIGRATE? e.g. does
> MIGRATE_INFO_TYPE return something other than 2 ("MP or not present")?

We are not require migrate and we don't need to keep CPU online now.
Migrate should return -1.

> 
> [...]
> 
>> +       amba_apu {
>> +               compatible = "simple-bus";
>> +               #address-cells = <2>;
>> +               #size-cells = <1>;
>> +               ranges;
>> +
>> +               timer {
>> +                       compatible = "arm,armv8-timer";
>> +                       interrupt-parent = <&gic>;
>> +                       interrupts = <1 13 0xff01>,
>> +                                    <1 14 0xff01>,
>> +                                    <1 11 0xff01>,
>> +                                    <1 10 0xff01>;
>> +               };
> 
> The architected timer should just be under the root node, given it's a
> component of the CPU -- it doesn't live on any bus.

Fair enough - will add it there.

> 
> I take it CNTFRQ is configured appropriately on all CPUs?

I believe so. :-)


> [...]
> 
>> +               i2c_clk: i2c_clk {
>> +                       compatible = "fixed-clock";
>> +                       #clock-cells = <0x0>;
>> +                       clock-frequency = <111111111>;
>> +               };
> 
> That clock-frequency looks a little odd. Is that right?

why is it odd? Is value too high?
It is exactly what we need to get to get i2c working.

> 
> I haven't taken an in-depth look at the other nodes. They look sane at a
> high-level, and assuming they are all already documented and supported
> they look fine to me.

I was checking that and hopefully I didn't miss anything.

Thanks,
Michal

Patch
diff mbox

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 1b8e97331ffb..9f805cf2e0b0 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -228,6 +228,11 @@  config ARCH_XGENE
 	help
 	  This enables support for AppliedMicro X-Gene SOC Family
 
+config ARCH_ZYNQMP
+	bool "Xilinx ZynqMP Family"
+	help
+	  This enables support for Xilinx ZynqMP Family
+
 endmenu
 
 menu "Bus support"
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e0350caf049e..ff088ec6ca5f 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -5,5 +5,6 @@  dts-dirs += cavium
 dts-dirs += exynos
 dts-dirs += freescale
 dts-dirs += mediatek
+dts-dirs += xilinx
 
 subdir-y	:= $(dts-dirs)
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
new file mode 100644
index 000000000000..ae16427f6a4a
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -0,0 +1,5 @@ 
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
+
+always		:= $(dtb-y)
+subdir-y	:= $(dts-dirs)
+clean-files	:= *.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
new file mode 100644
index 000000000000..121a47fb4043
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -0,0 +1,46 @@ 
+/*
+ * dts file for Xilinx ZynqMP ep108 development board
+ *
+ * (c) Copyright 2014 - 2015, Xilinx, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+/include/ "zynqmp.dtsi"
+
+/ {
+	model = "ZynqMP EP108";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x40000000>;
+	};
+};
+
+&gem0 {
+	status = "okay";
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	phy0: phy@0{
+		reg = <0>;
+		max-speed = <100>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
new file mode 100644
index 000000000000..d8402fd2dffa
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -0,0 +1,301 @@ 
+/*
+ * dts file for Xilinx ZynqMP
+ *
+ * (c) Copyright 2014 - 2015, Xilinx, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/ {
+	compatible = "xlnx,zynqmp";
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x0>;
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x1>;
+		};
+
+		cpu@2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x2>;
+		};
+
+		cpu@3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x3>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <0 143 4>,
+			     <0 144 4>,
+			     <0 145 4>,
+			     <0 146 4>;
+	};
+
+	amba_apu {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		timer {
+			compatible = "arm,armv8-timer";
+			interrupt-parent = <&gic>;
+			interrupts = <1 13 0xff01>,
+				     <1 14 0xff01>,
+				     <1 11 0xff01>,
+				     <1 10 0xff01>;
+		};
+
+		gic: interrupt-controller@f9010000 {
+			compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			reg = <0x0 0xf9010000 0x10000>,
+			      <0x0 0xf9020000 0x20000>,
+			      <0x0 0xf9040000 0x20000>,
+			      <0x0 0xf9060000 0x20000>;
+			interrupt-controller;
+		};
+	};
+
+	amba {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		misc_clk: misc_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+
+		ttc0: timer@ff110000 {
+			compatible = "cdns,ttc";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
+			reg = <0x0 0xff110000 0x1000>;
+			clocks = <&misc_clk>;
+			timer-width = <32>;
+		};
+
+		ttc1: timer@ff120000 {
+			compatible = "cdns,ttc";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
+			reg = <0x0 0xff120000 0x1000>;
+			clocks = <&misc_clk>;
+			timer-width = <32>;
+		};
+
+		ttc2: timer@ff130000 {
+			compatible = "cdns,ttc";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
+			reg = <0x0 0xff130000 0x1000>;
+			clocks = <&misc_clk>;
+			timer-width = <32>;
+		};
+
+		ttc3: timer@ff140000 {
+			compatible = "cdns,ttc";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
+			reg = <0x0 0xff140000 0x1000>;
+			clocks = <&misc_clk>;
+			timer-width = <32>;
+		};
+
+		uart0: serial@ff000000 {
+			compatible = "cdns,uart-r1p8";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 21 4>;
+			reg = <0x0 0xff000000 0x1000>;
+			clock-names = "uart_clk", "pclk";
+			clocks = <&misc_clk &misc_clk>;
+		};
+
+		uart1: serial@ff010000 {
+			compatible = "cdns,uart-r1p8";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 22 4>;
+			reg = <0x0 0xff010000 0x1000>;
+			clock-names = "uart_clk", "pclk";
+			clocks = <&misc_clk &misc_clk>;
+		};
+
+		gpio: gpio@ff0a0000 {
+			compatible = "xlnx,zynq-gpio-1.0";
+			status = "disabled";
+			#gpio-cells = <0x2>;
+			clocks = <&misc_clk>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 16 4>;
+			reg = <0x0 0xff0a0000 0x1000>;
+		};
+
+		gem0: ethernet@ff0b0000 {
+			compatible = "cdns,gem";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 57 4>;
+			reg = <0x0 0xff0b0000 0x1000>;
+			clock-names = "pclk", "hclk", "tx_clk";
+			clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		gem1: ethernet@ff0c0000 {
+			compatible = "cdns,gem";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 59 4>;
+			reg = <0x0 0xff0c0000 0x1000>;
+			clock-names = "pclk", "hclk", "tx_clk";
+			clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		gem2: ethernet@ff0d0000 {
+			compatible = "cdns,gem";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 61 4>;
+			reg = <0x0 0xff0d0000 0x1000>;
+			clock-names = "pclk", "hclk", "tx_clk";
+			clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		gem3: ethernet@ff0e0000 {
+			compatible = "cdns,gem";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 63 4>;
+			reg = <0x0 0xff0e0000 0x1000>;
+			clock-names = "pclk", "hclk", "tx_clk";
+			clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi0: spi@ff040000 {
+			compatible = "cdns,spi-r1p6";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 19 4>;
+			reg = <0x0 0xff040000 0x1000>;
+			clock-names = "ref_clk", "pclk";
+			clocks = <&misc_clk &misc_clk>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@ff050000 {
+			compatible = "cdns,spi-r1p6";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 20 4>;
+			reg = <0x0 0xff050000 0x1000>;
+			clock-names = "ref_clk", "pclk";
+			clocks = <&misc_clk &misc_clk>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c_clk: i2c_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <111111111>;
+		};
+
+		i2c0: i2c@ff020000 {
+			compatible = "cdns,i2c-r1p10";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 17 4>;
+			reg = <0x0 0xff020000 0x1000>;
+			clocks = <&i2c_clk>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@ff030000 {
+			compatible = "cdns,i2c-r1p10";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 18 4>;
+			reg = <0x0 0xff030000 0x1000>;
+			clocks = <&i2c_clk>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		sdhci0: sdhci@ff160000 {
+			compatible = "arasan,sdhci-8.9a";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 48 4>;
+			reg = <0x0 0xff160000 0x1000>;
+			clock-names = "clk_xin", "clk_ahb";
+			clocks = <&misc_clk>, <&misc_clk>;
+		};
+
+		sdhci1: sdhci@ff170000 {
+			compatible = "arasan,sdhci-8.9a";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 49 4>;
+			reg = <0x0 0xff170000 0x1000>;
+			clock-names = "clk_xin", "clk_ahb";
+			clocks = <&misc_clk>, <&misc_clk>;
+		};
+
+		watchdog0: watchdog@fd4d0000 {
+			compatible = "cdns,wdt-r1p2";
+			status = "disabled";
+			clocks= <&misc_clk>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 52 1>;
+			reg = <0x0 0xfd4d0000 0x1000>;
+			timeout-sec = <10>;
+		};
+	};
+};
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index be1f12a5a5f0..4ffe4c951416 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -36,6 +36,7 @@  CONFIG_ARCH_MEDIATEK=y
 CONFIG_ARCH_THUNDER=y
 CONFIG_ARCH_VEXPRESS=y
 CONFIG_ARCH_XGENE=y
+CONFIG_ARCH_ZYNQMP=y
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_XGENE=y