diff mbox

[v9,1/5] Documentation: Add device tree bindings for Freescale i.MX GPC

Message ID 1424713215-3357-2-git-send-email-p.zabel@pengutronix.de
State Accepted, archived
Commit 58e4a668be82362c32577ef08e06c8a292e3a457
Headers show

Commit Message

Philipp Zabel Feb. 23, 2015, 5:40 p.m. UTC 
The i.MX6 contains a power controller that controls power gating and
sequencing for the SoC's power domains.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
Changes since v8:
 - Updated example with IRQ_TYPE_... and IMX6QDL_CLK_... defines
---
 .../devicetree/bindings/power/fsl,imx-gpc.txt      | 59 ++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/fsl,imx-gpc.txt

Comments

Shawn Guo March 3, 2015, 2:35 a.m. UTC | #1 
On Mon, Feb 23, 2015 at 06:40:11PM +0100, Philipp Zabel wrote:
> The i.MX6 contains a power controller that controls power gating and
> sequencing for the SoC's power domains.
> 
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

The patch (series) looks fine to me.  Can we get DT maintainer's ACK on
this, so that I can apply the series for 4.1?

Shawn

> ---
> Changes since v8:
>  - Updated example with IRQ_TYPE_... and IMX6QDL_CLK_... defines
> ---
>  .../devicetree/bindings/power/fsl,imx-gpc.txt      | 59 ++++++++++++++++++++++
>  1 file changed, 59 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
> 
> diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
> new file mode 100644
> index 0000000..65cc034
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
> @@ -0,0 +1,59 @@
> +Freescale i.MX General Power Controller
> +=======================================
> +
> +The i.MX6Q General Power Control (GPC) block contains DVFS load tracking
> +counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power
> +domains.
> +
> +Required properties:
> +- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc"
> +- reg: should be register base and length as documented in the
> +  datasheet
> +- interrupts: Should contain GPC interrupt request 1
> +- pu-supply: Link to the LDO regulator powering the PU power domain
> +- clocks: Clock phandles to devices in the PU power domain that need
> +	  to be enabled during domain power-up for reset propagation.
> +- #power-domain-cells: Should be 1, see below:
> +
> +The gpc node is a power-controller as documented by the generic power domain
> +bindings in Documentation/devicetree/bindings/power/power_domain.txt.
> +
> +Example:
> +
> +	gpc: gpc@020dc000 {
> +		compatible = "fsl,imx6q-gpc";
> +		reg = <0x020dc000 0x4000>;
> +		interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
> +			     <0 90 IRQ_TYPE_LEVEL_HIGH>;
> +		pu-supply = <&reg_pu>;
> +		clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
> +			 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
> +			 <&clks IMX6QDL_CLK_GPU2D_CORE>,
> +			 <&clks IMX6QDL_CLK_GPU2D_AXI>,
> +			 <&clks IMX6QDL_CLK_OPENVG_AXI>,
> +			 <&clks IMX6QDL_CLK_VPU_AXI>;
> +		#power-domain-cells = <1>;
> +	};
> +
> +
> +Specifying power domain for IP modules
> +======================================
> +
> +IP cores belonging to a power domain should contain a 'power-domains' property
> +that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying
> +the power domain the device belongs to.
> +
> +Example of a device that is part of the PU power domain:
> +
> +	vpu: vpu@02040000 {
> +		reg = <0x02040000 0x3c000>;
> +		/* ... */
> +		power-domains = <&gpc 1>;
> +		/* ... */
> +	};
> +
> +The following DOMAIN_INDEX values are valid for i.MX6Q:
> +ARM_DOMAIN     0
> +PU_DOMAIN      1
> +The following additional DOMAIN_INDEX value is valid for i.MX6SL:
> +DISPLAY_DOMAIN 2
> -- 
> 2.1.4
> 
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Lucas Stach April 22, 2015, 10:34 a.m. UTC | #2 
Am Dienstag, den 03.03.2015, 10:35 +0800 schrieb Shawn Guo:
> On Mon, Feb 23, 2015 at 06:40:11PM +0100, Philipp Zabel wrote:
> > The i.MX6 contains a power controller that controls power gating and
> > sequencing for the SoC's power domains.
> > 
> > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> 
> The patch (series) looks fine to me.  Can we get DT maintainer's ACK on
> this, so that I can apply the series for 4.1?
> 
> Shawn
> 
I'm formally NACKing this series.

I've talked to Philipp and we decided to change the DT binding slightly
to better accommodate SoCs with multiple domains like the imx6sx.

I will send a new version of this series shortly.

Regards,
Lucas

> > ---
> > Changes since v8:
> >  - Updated example with IRQ_TYPE_... and IMX6QDL_CLK_... defines
> > ---
> >  .../devicetree/bindings/power/fsl,imx-gpc.txt      | 59 ++++++++++++++++++++++
> >  1 file changed, 59 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
> > new file mode 100644
> > index 0000000..65cc034
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
> > @@ -0,0 +1,59 @@
> > +Freescale i.MX General Power Controller
> > +=======================================
> > +
> > +The i.MX6Q General Power Control (GPC) block contains DVFS load tracking
> > +counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power
> > +domains.
> > +
> > +Required properties:
> > +- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc"
> > +- reg: should be register base and length as documented in the
> > +  datasheet
> > +- interrupts: Should contain GPC interrupt request 1
> > +- pu-supply: Link to the LDO regulator powering the PU power domain
> > +- clocks: Clock phandles to devices in the PU power domain that need
> > +	  to be enabled during domain power-up for reset propagation.
> > +- #power-domain-cells: Should be 1, see below:
> > +
> > +The gpc node is a power-controller as documented by the generic power domain
> > +bindings in Documentation/devicetree/bindings/power/power_domain.txt.
> > +
> > +Example:
> > +
> > +	gpc: gpc@020dc000 {
> > +		compatible = "fsl,imx6q-gpc";
> > +		reg = <0x020dc000 0x4000>;
> > +		interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
> > +			     <0 90 IRQ_TYPE_LEVEL_HIGH>;
> > +		pu-supply = <&reg_pu>;
> > +		clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
> > +			 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
> > +			 <&clks IMX6QDL_CLK_GPU2D_CORE>,
> > +			 <&clks IMX6QDL_CLK_GPU2D_AXI>,
> > +			 <&clks IMX6QDL_CLK_OPENVG_AXI>,
> > +			 <&clks IMX6QDL_CLK_VPU_AXI>;
> > +		#power-domain-cells = <1>;
> > +	};
> > +
> > +
> > +Specifying power domain for IP modules
> > +======================================
> > +
> > +IP cores belonging to a power domain should contain a 'power-domains' property
> > +that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying
> > +the power domain the device belongs to.
> > +
> > +Example of a device that is part of the PU power domain:
> > +
> > +	vpu: vpu@02040000 {
> > +		reg = <0x02040000 0x3c000>;
> > +		/* ... */
> > +		power-domains = <&gpc 1>;
> > +		/* ... */
> > +	};
> > +
> > +The following DOMAIN_INDEX values are valid for i.MX6Q:
> > +ARM_DOMAIN     0
> > +PU_DOMAIN      1
> > +The following additional DOMAIN_INDEX value is valid for i.MX6SL:
> > +DISPLAY_DOMAIN 2
> > -- 
> > 2.1.4
> > 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
new file mode 100644
index 0000000..65cc034
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
@@ -0,0 +1,59 @@ 
+Freescale i.MX General Power Controller
+=======================================
+
+The i.MX6Q General Power Control (GPC) block contains DVFS load tracking
+counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power
+domains.
+
+Required properties:
+- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc"
+- reg: should be register base and length as documented in the
+  datasheet
+- interrupts: Should contain GPC interrupt request 1
+- pu-supply: Link to the LDO regulator powering the PU power domain
+- clocks: Clock phandles to devices in the PU power domain that need
+	  to be enabled during domain power-up for reset propagation.
+- #power-domain-cells: Should be 1, see below:
+
+The gpc node is a power-controller as documented by the generic power domain
+bindings in Documentation/devicetree/bindings/power/power_domain.txt.
+
+Example:
+
+	gpc: gpc@020dc000 {
+		compatible = "fsl,imx6q-gpc";
+		reg = <0x020dc000 0x4000>;
+		interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 90 IRQ_TYPE_LEVEL_HIGH>;
+		pu-supply = <&reg_pu>;
+		clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+			 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+			 <&clks IMX6QDL_CLK_GPU2D_CORE>,
+			 <&clks IMX6QDL_CLK_GPU2D_AXI>,
+			 <&clks IMX6QDL_CLK_OPENVG_AXI>,
+			 <&clks IMX6QDL_CLK_VPU_AXI>;
+		#power-domain-cells = <1>;
+	};
+
+
+Specifying power domain for IP modules
+======================================
+
+IP cores belonging to a power domain should contain a 'power-domains' property
+that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying
+the power domain the device belongs to.
+
+Example of a device that is part of the PU power domain:
+
+	vpu: vpu@02040000 {
+		reg = <0x02040000 0x3c000>;
+		/* ... */
+		power-domains = <&gpc 1>;
+		/* ... */
+	};
+
+The following DOMAIN_INDEX values are valid for i.MX6Q:
+ARM_DOMAIN     0
+PU_DOMAIN      1
+The following additional DOMAIN_INDEX value is valid for i.MX6SL:
+DISPLAY_DOMAIN 2