Message ID | 1424702099-7799-1-git-send-email-m.cavallini@koansoftware.com |
---|---|
State | Changes Requested |
Delegated to: | Stefano Babic |
Headers | show |
Hi Marco, On Mon, Feb 23, 2015 at 11:34 AM, Marco Cavallini <m.cavallini@koansoftware.com> wrote: Please provide a commit log. > Signed-off-by: Marco Cavallini <m.cavallini@koansoftware.com> > --- > arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c > index a744e5d..9e11288 100644 > --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c > +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c > @@ -315,9 +315,27 @@ static void mx28_mem_init(void) > > debug("SPL: Initialising mx28 SDRAM Controller\n"); > > +#ifndef CONFIG_SYS_MXS_mDDR Currently there is no user for this config option. I suggest that you document it and add a board that makes use of it. Regards, Fabio Estevam
Hi Marco, On 23/02/2015 15:34, Marco Cavallini wrote: > > Signed-off-by: Marco Cavallini <m.cavallini@koansoftware.com> > --- > arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c > index a744e5d..9e11288 100644 > --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c > +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c > @@ -315,9 +315,27 @@ static void mx28_mem_init(void) > > debug("SPL: Initialising mx28 SDRAM Controller\n"); > > +#ifndef CONFIG_SYS_MXS_mDDR > /* Set DDR2 mode */ > writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, > &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); > +#else > + /* Set mDDR mode */ > + writel( PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK | > + PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK | > + PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK | > + PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK | > + PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK | > + PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK | > + PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK, > + &pinctrl_regs->hw_pinctrl_emi_ds_ctrl); > + > + /* Configure Pins 0-15 as EMI pins */ > + writel(0, &pinctrl_regs->hw_pinctrl_muxsel10); > + writel(0, &pinctrl_regs->hw_pinctrl_muxsel11); > + writel(0, &pinctrl_regs->hw_pinctrl_muxsel12); > + writel(0, &pinctrl_regs->hw_pinctrl_muxsel13); > +#endif The thing is that there is no use case in mainline, because no board is using it. To avoid that the issue is completely hidden, I suggest to add at least documentation for CONFIG_SYS_MXS_mDDR in README. If someone else will use mDDR, it will be easy to find how. Best regards, Stefano Babic
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index a744e5d..9e11288 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -315,9 +315,27 @@ static void mx28_mem_init(void) debug("SPL: Initialising mx28 SDRAM Controller\n"); +#ifndef CONFIG_SYS_MXS_mDDR /* Set DDR2 mode */ writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); +#else + /* Set mDDR mode */ + writel( PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK | + PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK | + PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK | + PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK | + PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK | + PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK | + PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK, + &pinctrl_regs->hw_pinctrl_emi_ds_ctrl); + + /* Configure Pins 0-15 as EMI pins */ + writel(0, &pinctrl_regs->hw_pinctrl_muxsel10); + writel(0, &pinctrl_regs->hw_pinctrl_muxsel11); + writel(0, &pinctrl_regs->hw_pinctrl_muxsel12); + writel(0, &pinctrl_regs->hw_pinctrl_muxsel13); +#endif /* * Configure the DRAM registers
Signed-off-by: Marco Cavallini <m.cavallini@koansoftware.com> --- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)