@@ -37,6 +37,6 @@ CONFIG_DM_SERIAL=y
CONFIG_UNIPHIER_SERIAL=y
CONFIG_DM_I2C=y
CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_XHCI_HCD=y
CONFIG_USB_STORAGE=y
S:CONFIG_SPL_NAND_DENALI=y
@@ -88,6 +88,8 @@
/* #define CONFIG_SYS_ICACHE_OFF */
/* #define CONFIG_SYS_DCACHE_OFF */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
/* Comment out the following to enable L2 cache */
#define CONFIG_UNIPHIER_L2CACHE_ON
@@ -186,6 +188,7 @@
/* USB */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
#define CONFIG_DOS_PARTITION
PH1-Pro4 includes both EHCI and xHCI IP cores. Unfortunately, U-Boot cannot enable EHCI and xHCI support simultaneously. Some users may wish Super-Speed connection. Disable CONFIG_USB_EHCI_HCD and enable CONFIG_USB_XHCI_HCD. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> --- Changes in v3: None Changes in v2: None configs/ph1_pro4_defconfig | 2 +- include/configs/uniphier.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-)