@@ -876,21 +876,10 @@ build_ssdt(GArray *table_data, GArray *linker,
aml_word_io(aml_min_fixed, aml_max_fixed,
aml_pos_decode, aml_entire_range,
0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
- if (ich9_lpc_find()) { /* Q35 */
- aml_append(crs,
- aml_word_io(aml_min_fixed, aml_max_fixed,
- aml_pos_decode, aml_entire_range,
- 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300));
- } else { /* piix4 */
- aml_append(crs,
- aml_word_io(aml_min_fixed, aml_max_fixed,
- aml_pos_decode, aml_entire_range,
- 0x0000, 0x0D00, 0xAFDF, 0x0000, 0xA2E0));
- aml_append(crs,
- aml_word_io(aml_min_fixed, aml_max_fixed,
- aml_pos_decode, aml_entire_range,
- 0x0000, 0xAFE4, 0xFFFF, 0x0000, 0x501C));
- }
+ aml_append(crs,
+ aml_word_io(aml_min_fixed, aml_max_fixed,
+ aml_pos_decode, aml_entire_range,
+ 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300));
aml_append(crs,
aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
aml_cacheable, aml_ReadWrite,
@@ -909,6 +898,19 @@ build_ssdt(GArray *table_data, GArray *linker,
}
aml_append(scope, aml_name_decl("_CRS", crs));
+ /* reserve GPE0 block resources */
+ dev = aml_device("GPE0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
+ aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
+ /* device present, functioning, decoding, not shown in UI */
+ aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_io(aml_decode16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
+ );
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+
/* reserve PCIHP resources */
if (pm->pcihp_io_len) {
dev = aml_device("PHPR");
Drops manual hole punching in PCI0._CRS on PIIX4 machine type for GPE0 resources. Resources will be consumed by Device(GPE0) that is attached to PCI namespace. There is GPE device with HID ACPI0006 since ACPI2.0 that should be used for this purpose but none of Windows versions support it and show it as "unknown device", so reserve resource in old fashioned way with PNP0A06 device to make windows happy and actually reserve resources. Along with last hole _CRS layout of PIIX4 machine becomes the same as Q35 one, so merge them together and use the same _CRS for both machine types. Signed-off-by: Igor Mammedov <imammedo@redhat.com> --- hw/i386/acpi-build.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-)