| Message ID | 1424271115-7885-3-git-send-email-leon.alrae@imgtec.com |
|---|---|
| State | New |
| Headers | show |
On 02/18/2015 06:51 AM, Leon Alrae wrote: > static VMStateField vmstate_fpu_fields[] = { > VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32), > - VMSTATE_INT8(fp_status.float_detect_tininess, CPUMIPSFPUContext), > + VMSTATE_UINT8(fp_status.flush_to_zero, CPUMIPSFPUContext), > VMSTATE_INT8(fp_status.float_rounding_mode, CPUMIPSFPUContext), > VMSTATE_INT8(fp_status.float_exception_flags, CPUMIPSFPUContext), > VMSTATE_UINT32(fcr0, CPUMIPSFPUContext), > @@ -70,6 +78,11 @@ static VMStateField vmstate_tc_fields[] = { > VMSTATE_UINTTL(CP0_TCScheFBack, TCState), > VMSTATE_INT32(CP0_Debug_tcstatus, TCState), > VMSTATE_UINTTL(CP0_UserLocal, TCState), > + VMSTATE_INT32(msacsr, TCState), > + VMSTATE_INT8(msa_fp_status.float_rounding_mode, TCState), > + VMSTATE_INT8(msa_fp_status.float_exception_flags, TCState), > + VMSTATE_UINT8(msa_fp_status.flush_to_zero, TCState), > + VMSTATE_UINT8(msa_fp_status.flush_inputs_to_zero, TCState), > VMSTATE_END_OF_LIST() > }; Surely these fp_status fields are simply implementation of the architectural CSR registers? IMO you shouldn't store things related to TCG state, but always how the architecture represents it. That way you're free to change the TCG implementation without breaking save/restore. r~
On 19/02/2015 15:43, Richard Henderson wrote: > On 02/18/2015 06:51 AM, Leon Alrae wrote: >> static VMStateField vmstate_fpu_fields[] = { >> VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32), >> - VMSTATE_INT8(fp_status.float_detect_tininess, CPUMIPSFPUContext), >> + VMSTATE_UINT8(fp_status.flush_to_zero, CPUMIPSFPUContext), >> VMSTATE_INT8(fp_status.float_rounding_mode, CPUMIPSFPUContext), >> VMSTATE_INT8(fp_status.float_exception_flags, CPUMIPSFPUContext), >> VMSTATE_UINT32(fcr0, CPUMIPSFPUContext), >> @@ -70,6 +78,11 @@ static VMStateField vmstate_tc_fields[] = { >> VMSTATE_UINTTL(CP0_TCScheFBack, TCState), >> VMSTATE_INT32(CP0_Debug_tcstatus, TCState), >> VMSTATE_UINTTL(CP0_UserLocal, TCState), >> + VMSTATE_INT32(msacsr, TCState), >> + VMSTATE_INT8(msa_fp_status.float_rounding_mode, TCState), >> + VMSTATE_INT8(msa_fp_status.float_exception_flags, TCState), >> + VMSTATE_UINT8(msa_fp_status.flush_to_zero, TCState), >> + VMSTATE_UINT8(msa_fp_status.flush_inputs_to_zero, TCState), >> VMSTATE_END_OF_LIST() >> }; > > Surely these fp_status fields are simply implementation of the architectural > CSR registers? > > IMO you shouldn't store things related to TCG state, but always how the > architecture represents it. That way you're free to change the TCG > implementation without breaking save/restore. Good point. Saving fp_status and msa_fp_status doesn't seem to be needed at all as they can be restored from FCSR and MSACSR respectively. Presumably I can use vmstate post_load() for that. Thanks, Leon
On Thu, 19 Feb 2015, Leon Alrae wrote: > > Surely these fp_status fields are simply implementation of the architectural > > CSR registers? > > > > IMO you shouldn't store things related to TCG state, but always how the > > architecture represents it. That way you're free to change the TCG > > implementation without breaking save/restore. > > Good point. Saving fp_status and msa_fp_status doesn't seem to be needed > at all as they can be restored from FCSR and MSACSR respectively. Agreed. Richard, thanks for the suggestion! Maciej
diff --git a/target-mips/machine.c b/target-mips/machine.c index 8d75962..c08e593 100644 --- a/target-mips/machine.c +++ b/target-mips/machine.c @@ -6,15 +6,23 @@ static int get_fpr(QEMUFile *f, void *pv, size_t size) { + int i; fpr_t *v = pv; - qemu_get_be64s(f, &v->d); + /* Restore entire MSA vector register */ + for (i = 0; i < MSA_WRLEN/64; i++) { + qemu_get_sbe64s(f, &v->wr.d[i]); + } return 0; } static void put_fpr(QEMUFile *f, void *pv, size_t size) { + int i; fpr_t *v = pv; - qemu_put_be64s(f, &v->d); + /* Save entire MSA vector register */ + for (i = 0; i < MSA_WRLEN/64; i++) { + qemu_put_sbe64s(f, &v->wr.d[i]); + } } const VMStateInfo vmstate_info_fpr = { @@ -31,7 +39,7 @@ const VMStateInfo vmstate_info_fpr = { static VMStateField vmstate_fpu_fields[] = { VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32), - VMSTATE_INT8(fp_status.float_detect_tininess, CPUMIPSFPUContext), + VMSTATE_UINT8(fp_status.flush_to_zero, CPUMIPSFPUContext), VMSTATE_INT8(fp_status.float_rounding_mode, CPUMIPSFPUContext), VMSTATE_INT8(fp_status.float_exception_flags, CPUMIPSFPUContext), VMSTATE_UINT32(fcr0, CPUMIPSFPUContext), @@ -70,6 +78,11 @@ static VMStateField vmstate_tc_fields[] = { VMSTATE_UINTTL(CP0_TCScheFBack, TCState), VMSTATE_INT32(CP0_Debug_tcstatus, TCState), VMSTATE_UINTTL(CP0_UserLocal, TCState), + VMSTATE_INT32(msacsr, TCState), + VMSTATE_INT8(msa_fp_status.float_rounding_mode, TCState), + VMSTATE_INT8(msa_fp_status.float_exception_flags, TCState), + VMSTATE_UINT8(msa_fp_status.flush_to_zero, TCState), + VMSTATE_UINT8(msa_fp_status.flush_inputs_to_zero, TCState), VMSTATE_END_OF_LIST() }; @@ -183,8 +196,8 @@ const VMStateDescription vmstate_tlb = { const VMStateDescription vmstate_mips_cpu = { .name = "cpu", - .version_id = 5, - .minimum_version_id = 5, + .version_id = 6, + .minimum_version_id = 6, .fields = (VMStateField[]) { /* active TC */ VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),
Correct the structure and store MSA and FP flush_to_zero. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> --- target-mips/machine.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-)