From patchwork Sat Jan 30 19:49:44 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartlomiej Zolnierkiewicz X-Patchwork-Id: 44092 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id AF438B7D35 for ; Sun, 31 Jan 2010 06:52:18 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753742Ab0A3Tt4 (ORCPT ); Sat, 30 Jan 2010 14:49:56 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1754441Ab0A3Ttz (ORCPT ); Sat, 30 Jan 2010 14:49:55 -0500 Received: from mail-fx0-f220.google.com ([209.85.220.220]:50554 "EHLO mail-fx0-f220.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752887Ab0A3Ttx (ORCPT ); Sat, 30 Jan 2010 14:49:53 -0500 Received: by mail-fx0-f220.google.com with SMTP id 20so2981155fxm.21 for ; Sat, 30 Jan 2010 11:49:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:date:message-id :in-reply-to:references:subject; bh=gBQ/GSuJ2VBs/aSKdoLqHIx5OnQLxsbebqQ7H6T3RYs=; b=GHvRTH52833ob7QZG/H1RiU1MpuyG5gFlw4MxToaAdiaLDDKTmfNcDRTV/ltgd605w R03B/OV/4UK7ovPBGFDncqdbenLf7q9iJFUt8UmOL/WMe9DDOrH94Mpfn3pwitDRj0yQ /KDUIItGBFUJLnYuwXnVJy3Abeh5k8msDbiAE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:date:message-id:in-reply-to:references:subject; b=JDA5b5xLtPGaEVACneCb7LbhHv9PkylZ60T2VbE13Rmt7BqBJqtXecU7lXYYKc8J3l Y1N1ZJ2NVYP7oTlyriNQzoGVTv4SbrNwsyNvTY0Dnm5MfBKQ2D5s4zljL3saVUcWgmjM 2SuX4dhC2E06mRlYuWs7VUc52LXrI4zIvCYSU= Received: by 10.223.14.194 with SMTP id h2mr2336457faa.14.1264880992242; Sat, 30 Jan 2010 11:49:52 -0800 (PST) Received: from ?127.0.0.1? (chello089079027028.chello.pl [89.79.27.28]) by mx.google.com with ESMTPS id 16sm1108006fxm.0.2010.01.30.11.49.51 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 30 Jan 2010 11:49:51 -0800 (PST) From: Bartlomiej Zolnierkiewicz To: linux-ide@vger.kernel.org Cc: Bartlomiej Zolnierkiewicz , linux-kernel@vger.kernel.org Date: Sat, 30 Jan 2010 20:49:44 +0100 Message-Id: <20100130194944.30779.95951.sendpatchset@localhost> In-Reply-To: <20100130194918.30779.25485.sendpatchset@localhost> References: <20100130194918.30779.25485.sendpatchset@localhost> Subject: [PATCH 4/9] [ata_]piix: move documentation to ata_piix.h Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org From: Bartlomiej Zolnierkiewicz Subject: [PATCH] [ata_]piix: move documentation to ata_piix.h Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/ata/ata_piix.c | 45 --------------------------------------------- drivers/ata/ata_piix.h | 46 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/ide/piix.c | 37 ------------------------------------- 3 files changed, 46 insertions(+), 82 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: b/drivers/ata/ata_piix.c =================================================================== --- a/drivers/ata/ata_piix.c +++ b/drivers/ata/ata_piix.c @@ -36,51 +36,6 @@ * as Documentation/DocBook/libata.* * * Hardware documentation available at http://developer.intel.com/ - * - * Documentation - * Publically available from Intel web site. Errata documentation - * is also publically available. As an aide to anyone hacking on this - * driver the list of errata that are relevant is below, going back to - * PIIX4. Older device documentation is now a bit tricky to find. - * - * The chipsets all follow very much the same design. The orginal Triton - * series chipsets do _not_ support independant device timings, but this - * is fixed in Triton II. With the odd mobile exception the chips then - * change little except in gaining more modes until SATA arrives. This - * driver supports only the chips with independant timing (that is those - * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix - * for the early chip drivers. - * - * Errata of note: - * - * Unfixable - * PIIX4 errata #9 - Only on ultra obscure hw - * ICH3 errata #13 - Not observed to affect real hw - * by Intel - * - * Things we must deal with - * PIIX4 errata #10 - BM IDE hang with non UDMA - * (must stop/start dma to recover) - * 440MX errata #15 - As PIIX4 errata #10 - * PIIX4 errata #15 - Must not read control registers - * during a PIO transfer - * 440MX errata #13 - As PIIX4 errata #15 - * ICH2 errata #21 - DMA mode 0 doesn't work right - * ICH0/1 errata #55 - As ICH2 errata #21 - * ICH2 spec c #9 - Extra operations needed to handle - * drive hotswap [NOT YET SUPPORTED] - * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary - * and must be dword aligned - * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 - * ICH7 errata #16 - MWDMA1 timings are incorrect - * - * Should have been BIOS fixed: - * 450NX: errata #19 - DMA hangs on old 450NX - * 450NX: errata #20 - DMA hangs on old 450NX - * 450NX: errata #25 - Corruption with DMA on old 450NX - * ICH3 errata #15 - IDE deadlock under high load - * (BIOS must set dev 31 fn 0 bit 23) - * ICH3 errata #18 - Don't use native mode */ #include Index: b/drivers/ata/ata_piix.h =================================================================== --- a/drivers/ata/ata_piix.h +++ b/drivers/ata/ata_piix.h @@ -1,3 +1,49 @@ +/* + * Documentation: + * Publically available from Intel web site. Errata documentation + * is also publically available. As an aide to anyone hacking on this + * driver the list of errata that are relevant is below, going back to + * PIIX4. Older device documentation is now a bit tricky to find. + * + * The chipsets all follow very much the same design. The orginal Triton + * series chipsets do _not_ support independant device timings, but this + * is fixed in Triton II. With the odd mobile exception the chips then + * change little except in gaining more modes until SATA arrives. This + * driver supports only the chips with independant timing (that is those + * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix + * for the early chip drivers. + * + * Errata of note: + * + * Unfixable + * PIIX4 errata #9 - Only on ultra obscure hw + * ICH3 errata #13 - Not observed to affect real hw + * by Intel + * + * Things we must deal with + * PIIX4 errata #10 - BM IDE hang with non UDMA + * (must stop/start dma to recover) + * 440MX errata #15 - As PIIX4 errata #10 + * PIIX4 errata #15 - Must not read control registers + * during a PIO transfer + * 440MX errata #13 - As PIIX4 errata #15 + * ICH2 errata #21 - DMA mode 0 doesn't work right + * ICH0/1 errata #55 - As ICH2 errata #21 + * ICH2 spec c #9 - Extra operations needed to handle + * drive hotswap [NOT YET SUPPORTED] + * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary + * and must be dword aligned + * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 + * ICH7 errata #16 - MWDMA1 timings are incorrect + * + * Should have been BIOS fixed: + * 450NX: errata #19 - DMA hangs on old 450NX + * 450NX: errata #20 - DMA hangs on old 450NX + * 450NX: errata #25 - Corruption with DMA on old 450NX + * ICH3 errata #15 - IDE deadlock under high load + * (BIOS must set dev 31 fn 0 bit 23) + * ICH3 errata #18 - Don't use native mode + */ struct ich_laptop { u16 device; Index: b/drivers/ide/piix.c =================================================================== --- a/drivers/ide/piix.c +++ b/drivers/ide/piix.c @@ -5,43 +5,6 @@ * Copyright (C) 2006-2007 MontaVista Software, Inc. * * May be copied or modified under the terms of the GNU General Public License - * - * Documentation: - * - * Publically available from Intel web site. Errata documentation - * is also publically available. As an aide to anyone hacking on this - * driver the list of errata that are relevant is below.going back to - * PIIX4. Older device documentation is now a bit tricky to find. - * - * Errata of note: - * - * Unfixable - * PIIX4 errata #9 - Only on ultra obscure hw - * ICH3 errata #13 - Not observed to affect real hw - * by Intel - * - * Things we must deal with - * PIIX4 errata #10 - BM IDE hang with non UDMA - * (must stop/start dma to recover) - * 440MX errata #15 - As PIIX4 errata #10 - * PIIX4 errata #15 - Must not read control registers - * during a PIO transfer - * 440MX errata #13 - As PIIX4 errata #15 - * ICH2 errata #21 - DMA mode 0 doesn't work right - * ICH0/1 errata #55 - As ICH2 errata #21 - * ICH2 spec c #9 - Extra operations needed to handle - * drive hotswap [NOT YET SUPPORTED] - * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary - * and must be dword aligned - * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 - * - * Should have been BIOS fixed: - * 450NX: errata #19 - DMA hangs on old 450NX - * 450NX: errata #20 - DMA hangs on old 450NX - * 450NX: errata #25 - Corruption with DMA on old 450NX - * ICH3 errata #15 - IDE deadlock under high load - * (BIOS must set dev 31 fn 0 bit 23) - * ICH3 errata #18 - Don't use native mode */ #include