[v2,1/2] arm: Add the cortex-a9 CPU to the a9mpcore device

This patch adds the Cortex-A9 ARM CPU to the A9MPCore.

The CPU is only created if the num-cpu property is set.

This patch allows the midr and reset-cbar properties to be set

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V2:
 - Rename num_cpus function to match QOM style
 - Connect all CPUs to the GIC
Changes since RFC:
 - Add passthrough support for 'has_el3'

 hw/cpu/a9mpcore.c         | 61 ++++++++++++++++++++++++++++++++++++++++++++++-
 include/hw/cpu/a9mpcore.h |  2 ++
 2 files changed, 62 insertions(+), 1 deletion(-)

On Tue, Feb 17, 2015 at 7:59 PM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> This patch adds the Cortex-A9 ARM CPU to the A9MPCore.
>
> The CPU is only created if the num-cpu property is set.
>
> This patch allows the midr and reset-cbar properties to be set
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> V2:
>  - Rename num_cpus function to match QOM style
>  - Connect all CPUs to the GIC
> Changes since RFC:
>  - Add passthrough support for 'has_el3'
>
>  hw/cpu/a9mpcore.c         | 61 ++++++++++++++++++++++++++++++++++++++++++++++-
>  include/hw/cpu/a9mpcore.h |  2 ++
>  2 files changed, 62 insertions(+), 1 deletion(-)
>
> diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
> index c09358c..d925b09 100644
> --- a/hw/cpu/a9mpcore.c
> +++ b/hw/cpu/a9mpcore.c
> @@ -9,6 +9,7 @@
>   */
>
>  #include "hw/cpu/a9mpcore.h"
> +#include "qapi/visitor.h"
>
>  static void a9mp_priv_set_irq(void *opaque, int irq, int level)
>  {
> @@ -17,10 +18,50 @@ static void a9mp_priv_set_irq(void *opaque, int irq, int level)
>      qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
>  }
>
> +static void a9mpcore_set_num_cpus(Object *obj, Visitor *v,
> +                                  void *opaque, const char *name,
> +                                  Error **errp)
> +{
> +    A9MPPrivState *s = A9MPCORE_PRIV(obj);
> +    ObjectClass *cpu_oc;
> +    Error *err = NULL;
> +    int i;
> +    int64_t value;
> +
> +    visit_type_int(v, &value, name, &err);
> +    if (err) {
> +        error_propagate(errp, err);
> +        return;
> +    }
> +    s->num_cpu = value;
> +
> +    s->cpu = g_new0(ARMCPU, s->num_cpu);
> +    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9");
> +
> +    for (i = 0; i < s->num_cpu; i++) {
> +        object_initialize(&s->cpu[i], sizeof(*s->cpu),
> +                          object_class_get_name(cpu_oc));
> +
> +        object_property_add_alias(obj, "midr", OBJECT(&s->cpu[i]),
> +                                  "midr", NULL);
> +        object_property_add_alias(obj, "reset-cbar", OBJECT(&s->cpu[i]),
> +                                  "reset-cbar", NULL);
> +        object_property_add_alias(obj, "has_el3", OBJECT(&s->cpu[i]),
> +                                  "has_el3", NULL);

Errors need to be &error_abort or propagated (probably the latter).

The real issue here is object_property_add_alias, will only work once
per container, so non-0th iterations of this loop will fail as the
property already exists on the container. Unless aliases are fixed to
support single-source-multiple-target this wont work. There are two
resolutions to this (if anyone has any opinions?):

1: Patch QOM to allow this (my preffered - I think what you have here
is a good use case).
2: Implement some sort of generalisation for a property that fans out
its setter to multiple targets (something we havent seen at all yet)
3: Go full manual here with device specific individual property
setters here in the device itself.

I have some half working code for number 1 i'll send early next week.

Regards,
Peter

> +    }
> +}
> +
>  static void a9mp_priv_initfn(Object *obj)
>  {
>      A9MPPrivState *s = A9MPCORE_PRIV(obj);
>
> +    object_property_add(obj, "num-cpu", "int",
> +                        NULL, a9mpcore_set_num_cpus,
> +                        NULL, NULL, NULL);
> +    /* Use this as the default */
> +    s->cpu = NULL;
> +    s->num_cpu = 1;
> +
>      memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000);
>      sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container);
>
> @@ -50,6 +91,17 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
>      Error *err = NULL;
>      int i;
>
> +    if (s->cpu) {
> +        for (i = 0; i < s->num_cpu; i++) {
> +            object_property_set_bool(OBJECT(&s->cpu[i]), true,
> +                                     "realized", &err);
> +            if (err) {
> +                error_propagate(errp, err);
> +                return;
> +            }
> +        }
> +    }
> +
>      scudev = DEVICE(&s->scu);
>      qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
>      object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
> @@ -75,6 +127,14 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
>      /* Pass through inbound GPIO lines to the GIC */
>      qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32);
>
> +    if (s->cpu) {
> +        for (i = 0; i < s->num_cpu; i++) {
> +            sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
> +                               qdev_get_gpio_in(DEVICE(&s->cpu[i]),
> +                               ARM_CPU_IRQ));
> +        }
> +    }
> +
>      gtimerdev = DEVICE(&s->gtimer);
>      qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu);
>      object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err);
> @@ -144,7 +204,6 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
>  }
>
>  static Property a9mp_priv_properties[] = {
> -    DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1),
>      /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
>       * IRQ lines (with another 32 internal). We default to 64+32, which
>       * is the number provided by the Cortex-A9MP test chip in the
> diff --git a/include/hw/cpu/a9mpcore.h b/include/hw/cpu/a9mpcore.h
> index 5d67ca2..b7d0bc7 100644
> --- a/include/hw/cpu/a9mpcore.h
> +++ b/include/hw/cpu/a9mpcore.h
> @@ -29,6 +29,8 @@ typedef struct A9MPPrivState {
>      MemoryRegion container;
>      uint32_t num_irq;
>
> +    ARMCPU *cpu;
> +
>      A9SCUState scu;
>      GICState gic;
>      A9GTimerState gtimer;
> --
> 2.1.1
>
>