[2/2] pinctrl: sh-pfc: r8a7791: Remove non existing GPIO pins
diff mbox

Message ID 1424115661-21928-2-git-send-email-laurent.pinchart+renesas@ideasonboard.com
State New
Headers show

Commit Message

Laurent Pinchart Feb. 16, 2015, 7:41 p.m. UTC
GPIO banks 1 and 7 are missing pins 26 to 31. Remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

Comments

Geert Uytterhoeven Feb. 16, 2015, 7:47 p.m. UTC | #1
On Mon, Feb 16, 2015 at 8:41 PM, Laurent Pinchart
<laurent.pinchart+renesas@ideasonboard.com> wrote:
> GPIO banks 1 and 7 are missing pins 26 to 31. Remove them.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

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Geert Uytterhoeven Feb. 16, 2015, 7:59 p.m. UTC | #2
Hi Laurent,

On Mon, Feb 16, 2015 at 8:41 PM, Laurent Pinchart
<laurent.pinchart+renesas@ideasonboard.com> wrote:
> GPIO banks 1 and 7 are missing pins 26 to 31. Remove them.

BTW, one intriguing thing is that the description for GPSR7 seems to suggest
that GP-7-26 to GP-7-31 do exist, but cannot be configured for a peripheral
function. But I cannot find an actual pin on the chip's package these GPIOs
are connected to.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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Sergei Shtylyov Feb. 25, 2015, 8:58 p.m. UTC | #3
On 02/16/2015 10:41 PM, Laurent Pinchart wrote:

> GPIO banks 1 and 7 are missing pins 26 to 31. Remove them.

> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

    This patch breaks the boot as well, please don't apply it yet. The same 
about R8A7790 patch. We're thinking about a proper fix...

WBR, Sergei

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Sergei Shtylyov March 1, 2015, 5:15 p.m. UTC | #4
Hello.

On 2/25/2015 11:58 PM, Sergei Shtylyov wrote:

>> GPIO banks 1 and 7 are missing pins 26 to 31. Remove them.

>> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

>     This patch breaks the boot as well, please don't apply it yet. The same
> about R8A7790 patch. We're thinking about a proper fix...

    Hopefully, such fix has been found and posted. You can now apply this 
series *after* that fix.

WBR, Sergei

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Linus Walleij March 6, 2015, 10:27 a.m. UTC | #5
On Mon, Feb 16, 2015 at 8:41 PM, Laurent Pinchart
<laurent.pinchart+renesas@ideasonboard.com> wrote:

> GPIO banks 1 and 7 are missing pins 26 to 31. Remove them.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Patch applied with Geert's ACK.

Yours,
Linus Walleij
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Patch
diff mbox

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index fdd2c8729791..f6bd7628f2c5 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -14,15 +14,30 @@ 
 #include "core.h"
 #include "sh_pfc.h"
 
+#define PORT_GP_26(bank, fn, sfx)					\
+	PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),	\
+	PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),	\
+	PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),	\
+	PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),	\
+	PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),	\
+	PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),	\
+	PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),	\
+	PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),	\
+	PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),	\
+	PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),	\
+	PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),	\
+	PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),	\
+	PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx)
+
 #define CPU_ALL_PORT(fn, sfx)						\
 	PORT_GP_32(0, fn, sfx),						\
-	PORT_GP_32(1, fn, sfx),						\
+	PORT_GP_26(1, fn, sfx),						\
 	PORT_GP_32(2, fn, sfx),						\
 	PORT_GP_32(3, fn, sfx),						\
 	PORT_GP_32(4, fn, sfx),						\
 	PORT_GP_32(5, fn, sfx),						\
 	PORT_GP_32(6, fn, sfx),						\
-	PORT_GP_32(7, fn, sfx)
+	PORT_GP_26(7, fn, sfx)
 
 enum {
 	PINMUX_RESERVED = 0,