From patchwork Fri Jan 29 16:06:41 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartlomiej Zolnierkiewicz X-Patchwork-Id: 43981 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 1E2B3B7D27 for ; Sat, 30 Jan 2010 03:18:41 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754534Ab0A2QHG (ORCPT ); Fri, 29 Jan 2010 11:07:06 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1754814Ab0A2QG7 (ORCPT ); Fri, 29 Jan 2010 11:06:59 -0500 Received: from mail-fx0-f220.google.com ([209.85.220.220]:53041 "EHLO mail-fx0-f220.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754447Ab0A2QGs (ORCPT ); Fri, 29 Jan 2010 11:06:48 -0500 Received: by mail-fx0-f220.google.com with SMTP id 20so2015120fxm.21 for ; Fri, 29 Jan 2010 08:06:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:date:message-id :in-reply-to:references:subject; bh=4d0zItk8czKRXRLKq18ePQAdSX2EASCcBgMiGjSXBaQ=; b=m4xUh9Nt8LImV5wbckN9F9eyo0+2khHPbT2Kj9y3ubSZh6ST+w+lUMIvgPGJHFl1k5 HDIzrcsRuP1zzDfiAvqhlOKSbbwiWMXOdFBPA6nKkGWtvlcdbtk9390L8CxwjWoILWrd 2reblfDQi98abtN1GpqTNVnjfbXCHp6R+6fzw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:date:message-id:in-reply-to:references:subject; b=k4cUoPZBInvb4GLAEt3bzi6cUS52qynWyFqRBusqwIcV9agV+Er9TBN2e8tqiFgstB S3fOOlO6mypUbjsDnhMSbaHdQdvPc3UiR4w3mhvi45VQoqeSw0k5ghaJVuGbIvIHWiRd XigwS6CebT64PBXYaJgUnlZO3dmPEQmCoE144= Received: by 10.223.77.141 with SMTP id g13mr790663fak.95.1264781207584; Fri, 29 Jan 2010 08:06:47 -0800 (PST) Received: from ?127.0.0.1? (chello089079027028.chello.pl [89.79.27.28]) by mx.google.com with ESMTPS id 15sm549749fxm.14.2010.01.29.08.06.46 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 29 Jan 2010 08:06:47 -0800 (PST) From: Bartlomiej Zolnierkiewicz To: linux-ide@vger.kernel.org Cc: Bartlomiej Zolnierkiewicz , linux-kernel@vger.kernel.org Date: Fri, 29 Jan 2010 17:06:41 +0100 Message-Id: <20100129160641.21495.77291.sendpatchset@localhost> In-Reply-To: <20100129160308.21495.14120.sendpatchset@localhost> References: <20100129160308.21495.14120.sendpatchset@localhost> Subject: [PATCH 33/68] pata_amd: move code to be re-used by ide2libata to pata_amd.h Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org From: Bartlomiej Zolnierkiewicz Subject: [PATCH] pata_amd: move code to be re-used by ide2libata to pata_amd.h Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/ata/pata_amd.c | 87 ---------------------------------------------- drivers/ata/pata_amd.h | 92 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 93 insertions(+), 86 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: b/drivers/ata/pata_amd.c =================================================================== --- a/drivers/ata/pata_amd.c +++ b/drivers/ata/pata_amd.c @@ -26,92 +26,7 @@ #define DRV_NAME "pata_amd" #define DRV_VERSION "0.4.1" -/** - * timing_setup - shared timing computation and load - * @ap: ATA port being set up - * @adev: drive being configured - * @offset: port offset - * @speed: target speed - * @clock: clock multiplier (number of times 33MHz for this part) - * - * Perform the actual timing set up for Nvidia or AMD PATA devices. - * The actual devices vary so they all call into this helper function - * providing the clock multipler and offset (because AMD and Nvidia put - * the ports at different locations). - */ - -static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock) -{ - static const unsigned char amd_cyc2udma[] = { - 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 - }; - - struct pci_dev *pdev = to_pci_dev(ap->host->dev); - struct ata_device *peer = ata_dev_pair(adev); - int dn = ap->port_no * 2 + adev->devno; - struct ata_timing at, apeer; - int T, UT; - const int amd_clock = 33333; /* KHz. */ - u8 t; - - T = 1000000000 / amd_clock; - UT = T; - if (clock >= 2) - UT = T / 2; - - ata_timing_compute(adev->id, speed, adev->pio_mode, &at, T, UT); - - if (peer) { - ata_timing_compute(peer->id, peer->pio_mode, - peer->pio_mode, &apeer, T, UT); - ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT); - } - - if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1; - if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15; - - /* - * Now do the setup work - */ - - /* Configure the address set up timing */ - pci_read_config_byte(pdev, offset + 0x0C, &t); - t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(at.setup, 1, 4) - 1) << ((3 - dn) << 1)); - pci_write_config_byte(pdev, offset + 0x0C , t); - - /* Configure the 8bit I/O timing */ - pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)), - ((clamp_val(at.act8b, 1, 16) - 1) << 4) | (clamp_val(at.rec8b, 1, 16) - 1)); - - /* Drive timing */ - pci_write_config_byte(pdev, offset + 0x08 + (3 - dn), - ((clamp_val(at.active, 1, 16) - 1) << 4) | (clamp_val(at.recover, 1, 16) - 1)); - - switch (clock) { - case 1: - t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03; - break; - - case 2: - t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03; - break; - - case 3: - t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03; - break; - - case 4: - t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03; - break; - - default: - return; - } - - /* UDMA timing */ - if (at.udma) - pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t); -} +#include "pata_amd.h" /** * amd_pre_reset - perform reset handling Index: b/drivers/ata/pata_amd.h =================================================================== --- /dev/null +++ b/drivers/ata/pata_amd.h @@ -0,0 +1,92 @@ + +/** + * timing_setup - shared timing computation and load + * @ap: ATA port being set up + * @adev: drive being configured + * @offset: port offset + * @speed: target speed + * @clock: clock multiplier (number of times 33MHz for this part) + * + * Perform the actual timing set up for Nvidia or AMD PATA devices. + * The actual devices vary so they all call into this helper function + * providing the clock multipler and offset (because AMD and Nvidia put + * the ports at different locations). + */ + +static void timing_setup(struct ata_port *ap, struct ata_device *adev, + int offset, int speed, int clock) +{ + static const unsigned char amd_cyc2udma[] = { + 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 + }; + + struct pci_dev *pdev = to_pci_dev(ap->host->dev); + struct ata_device *peer = ata_dev_pair(adev); + int dn = ap->port_no * 2 + adev->devno; + struct ata_timing at, apeer; + int T, UT; + const int amd_clock = 33333; /* KHz. */ + u8 t; + + T = 1000000000 / amd_clock; + UT = T; + if (clock >= 2) + UT = T / 2; + + ata_timing_compute(adev->id, speed, adev->pio_mode, &at, T, UT); + + if (peer) { + ata_timing_compute(peer->id, peer->pio_mode, + peer->pio_mode, &apeer, T, UT); + ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT); + } + + if (speed == XFER_UDMA_5 && amd_clock <= 33333) + at.udma = 1; + if (speed == XFER_UDMA_6 && amd_clock <= 33333) + at.udma = 15; + + /* + * Now do the setup work + */ + + /* Configure the address set up timing */ + pci_read_config_byte(pdev, offset + 0x0C, &t); + t = (t & ~(3 << ((3 - dn) << 1))) | + ((clamp_val(at.setup, 1, 4) - 1) << ((3 - dn) << 1)); + pci_write_config_byte(pdev, offset + 0x0C , t); + + /* Configure the 8bit I/O timing */ + pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)), + ((clamp_val(at.act8b, 1, 16) - 1) << 4) | + (clamp_val(at.rec8b, 1, 16) - 1)); + + /* Drive timing */ + pci_write_config_byte(pdev, offset + 0x08 + (3 - dn), + ((clamp_val(at.active, 1, 16) - 1) << 4) | + (clamp_val(at.recover, 1, 16) - 1)); + + switch (clock) { + case 1: + t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03; + break; + case 2: + t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) + : 0x03; + break; + case 3: + t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) + : 0x03; + break; + case 4: + t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) + : 0x03; + break; + default: + return; + } + + /* UDMA timing */ + if (at.udma) + pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t); +}