@@ -3,3 +3,7 @@ CONFIG_SPL=y
+S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_PEACH_PI=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CMD_CROS_EC=y
@@ -3,3 +3,7 @@ CONFIG_SPL=y
+S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_PEACH_PIT=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit"
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CMD_CROS_EC=y
@@ -7,3 +7,8 @@ CONFIG_DM=y
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_CROS_EC=y
+CONFIG_DM_CROS_EC=y
+CONFIG_CROS_EC_SANDBOX=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CMD_CROS_EC=y
@@ -3,3 +3,8 @@ CONFIG_SPL=y
+S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_SNOW=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
+CONFIG_CROS_EC=y
+CONFIG_DM_CROS_EC=y
+CONFIG_CROS_EC_I2C=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CMD_CROS_EC=y
@@ -0,0 +1,6 @@
+config CROS_EC_KEYB
+ bool "Enable Chrome OS EC keyboard support"
+ help
+ Most ARM Chromebooks use an EC to provide access to the keyboard.
+ Messages are used to request key scans from the EC and these are
+ then decoded into keys by this driver.
@@ -1,3 +1,49 @@
+config CMD_CROS_EC
+ bool "Enable crosec command"
+ depends on CROS_EC
+ help
+ Enable command-line access to the Chrome OS EC (Embedded
+ Controller). This provides the 'crosec' command which has
+ a number of sub-commands for performing EC tasks such as
+ updating its flash, accessing a small saved context area
+ and talking to the I2C bus behind the EC (if there is one).
+
+config CROS_EC
+ bool "Enable Chrome OS EC"
+ help
+ Enable access to the Chrome OS EC. This is a separate
+ microcontroller typically available on a SPI bus on Chromebooks. It
+ provides access to the keyboard, some internal storage and may
+ control access to the battery and main PMIC depending on the
+ device. You can use the 'crosec' command to access it.
+
+config CROS_EC_I2C
+ bool "Enable Chrome OS EC I2C driver"
+ depends on CROS_EC
+ help
+ Enable I2C access to the Chrome OS EC. This is used on older
+ ARM Chromebooks such as snow and spring before the standard bus
+ changed to SPI. The EC will accept commands across the I2C using
+ a special message protocol, and provide responses.
+
+config CROS_EC_LPC
+ bool "Enable Chrome OS EC LPC driver"
+ depends on CROS_EC
+ help
+ Enable I2C access to the Chrome OS EC. This is used on x86
+ Chromebooks such as link and falco. The keyboard is provided
+ through a legacy port interface, so on x86 machines the main
+ function of the EC is power and thermal management.
+
+config CROS_EC_SPI
+ bool "Enable Chrome OS EC SPI driver"
+ depends on CROS_EC
+ help
+ Enable SPI access to the Chrome OS EC. This is used on newer
+ ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
+ provides a faster and more robust interface than I2C but the bugs
+ are less interesting.
+
config DM_CROS_EC
bool "Enable Driver Model for Chrome OS EC"
depends on DM
@@ -5,5 +51,5 @@ config DM_CROS_EC
Enable driver model for the Chrome OS EC interface. This
allows the cros_ec SPI driver to operate with CONFIG_DM_SPI
but otherwise makes few changes. Since cros_ec also supports
- I2C and LPC (which don't support driver model yet), a full
+ LPC (which doesn't support driver model yet), a full
conversion is not yet possible.
@@ -24,9 +24,6 @@
#define CONFIG_POWER_TPS65090
/* Enable keyboard */
-#define CONFIG_CROS_EC /* CROS_EC protocol */
-#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */
-#define CONFIG_CMD_CROS_EC
#define CONFIG_KEYBOARD
#endif
@@ -43,7 +43,6 @@
#endif
#define CONFIG_POWER_TPS65090_EC
-#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_EXYNOS
@@ -43,7 +43,6 @@
#endif
#define CONFIG_POWER_TPS65090_EC
-#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_EXYNOS
@@ -141,9 +141,6 @@
#define CONFIG_BOOTARGS ""
-#define CONFIG_CROS_EC
-#define CONFIG_CMD_CROS_EC
-#define CONFIG_CROS_EC_SANDBOX
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_BOARD_LATE_INIT
@@ -166,7 +163,6 @@
#define LCD_BPP LCD_COLOR16
#define CONFIG_LCD_BMP_RLE8
-#define CONFIG_CROS_EC_KEYB
#define CONFIG_KEYBOARD
#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial,cros-ec-keyb\0" \
@@ -20,9 +20,7 @@
#include <configs/exynos5-dt-common.h>
-#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
#define CONFIG_POWER_TPS65090_I2C
-#define CONFIG_DM_CROS_EC
#define CONFIG_BOARD_COMMON
#define CONFIG_ARCH_EARLY_INIT_R
Since both I2C and SPI are converted to Kconfig, we can convert cros_ec to Kconfig for these buses. LPC will need to wait until driver mode PCI is available. Signed-off-by: Simon Glass <sjg@chromium.org> --- configs/peach-pi_defconfig | 4 ++++ configs/peach-pit_defconfig | 4 ++++ configs/sandbox_defconfig | 5 ++++ configs/snow_defconfig | 5 ++++ drivers/input/Kconfig | 6 +++++ drivers/misc/Kconfig | 48 ++++++++++++++++++++++++++++++++++++- include/configs/exynos5-dt-common.h | 3 --- include/configs/peach-pi.h | 1 - include/configs/peach-pit.h | 1 - include/configs/sandbox.h | 4 ---- include/configs/snow.h | 2 -- 11 files changed, 71 insertions(+), 12 deletions(-)