===================================================================
@@ -43,155 +43,7 @@ static int it8213_pre_reset(struct ata_l
return ata_sff_prereset(link, deadline);
}
-/**
- * it8213_cable_detect - check for 40/80 pin
- * @ap: Port
- *
- * Perform cable detection for the 8213 ATA interface. This is
- * different to the PIIX arrangement
- */
-
-static int it8213_cable_detect(struct ata_port *ap)
-{
- struct pci_dev *pdev = to_pci_dev(ap->host->dev);
- u8 tmp;
- pci_read_config_byte(pdev, 0x42, &tmp);
- if (tmp & 2) /* The initial docs are incorrect */
- return ATA_CBL_PATA40;
- return ATA_CBL_PATA80;
-}
-
-static void it8213_set_timings(struct ata_port *ap, struct ata_device *adev,
- u8 pio, bool use_mwdma)
-{
- struct pci_dev *dev = to_pci_dev(ap->host->dev);
- u8 master_port = ap->port_no ? 0x42 : 0x40;
- u16 master_data;
- int control = 0;
-
- /*
- * See Intel Document 298600-004 for the timing programing rules
- * for PIIX/ICH. The 8213 is a clone so very similar
- */
-
- static const /* ISP RTC */
- u8 timings[][2] = { { 0, 0 },
- { 0, 0 },
- { 1, 0 },
- { 2, 1 },
- { 2, 3 }, };
-
- if (pio > 1 || use_mwdma)
- control |= 1; /* TIME */
- if (ata_pio_need_iordy(adev) || use_mwdma)
- control |= 2; /* IE */
- /* Bit 2 is set for ATAPI on the IT8213 - reverse of ICH/PIIX */
- if (adev->class != ATA_DEV_ATA)
- control |= 4; /* PPE */
- /* If the drive MWDMA is faster than it can do PIO then
- we must force PIO into PIO0 */
- if (use_mwdma && adev->pio_mode < (XFER_PIO_0 + pio))
- /* Enable DMA timing only */
- control |= 8; /* PIO cycles in PIO0 */
-
- pci_read_config_word(dev, master_port, &master_data);
-
- /* Set PPE, IE, and TIME as appropriate */
- if (adev->devno == 0) {
- master_data &= 0xCCF0;
- master_data |= control;
- master_data |= (timings[pio][0] << 12) |
- (timings[pio][1] << 8);
- } else {
- u8 slave_data;
-
- master_data &= 0xFF0F;
- master_data |= (control << 4);
-
- /* Slave timing in separate register */
- pci_read_config_byte(dev, 0x44, &slave_data);
- slave_data &= 0xF0;
- slave_data |= (timings[pio][0] << 2) | timings[pio][1];
- pci_write_config_byte(dev, 0x44, slave_data);
- }
-
- master_data |= 0x4000; /* Ensure SITRE is set */
- pci_write_config_word(dev, master_port, master_data);
-}
-
-/**
- * it8213_set_piomode - Initialize host controller PATA PIO timings
- * @ap: Port whose timings we are configuring
- * @adev: Device whose timings we are configuring
- *
- * Set PIO mode for device, in host controller PCI config space.
- *
- * LOCKING:
- * None (inherited from caller).
- */
-
-static void it8213_set_piomode(struct ata_port *ap, struct ata_device *adev)
-{
- it8213_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0, 0);
-}
-
-/**
- * it8213_set_dmamode - Initialize host controller PATA DMA timings
- * @ap: Port whose timings we are configuring
- * @adev: Device to program
- *
- * Set UDMA/MWDMA mode for device, in host controller PCI config space.
- * This device is basically an ICH alike.
- *
- * LOCKING:
- * None (inherited from caller).
- */
-
-static void it8213_set_dmamode (struct ata_port *ap, struct ata_device *adev)
-{
- struct pci_dev *dev = to_pci_dev(ap->host->dev);
- u8 speed = adev->dma_mode;
- int devid = adev->devno;
- u8 udma_enable;
-
- pci_read_config_byte(dev, 0x48, &udma_enable);
-
- if (speed >= XFER_UDMA_0) {
- unsigned int udma = speed - XFER_UDMA_0;
- u16 udma_timing;
- u16 ideconf;
- int u_clock, u_speed;
-
- /* Clocks follow the PIIX style */
- u_speed = min(2 - (udma & 1), udma);
- if (udma > 4)
- u_clock = 0x1000; /* 100Mhz */
- else if (udma > 2)
- u_clock = 1; /* 66Mhz */
- else
- u_clock = 0; /* 33Mhz */
-
- udma_enable |= (1 << devid);
-
- /* Load the UDMA cycle time */
- pci_read_config_word(dev, 0x4A, &udma_timing);
- udma_timing &= ~(3 << (4 * devid));
- udma_timing |= u_speed << (4 * devid);
- pci_write_config_word(dev, 0x4A, udma_timing);
-
- /* Load the clock selection */
- pci_read_config_word(dev, 0x54, &ideconf);
- ideconf &= ~(0x1001 << devid);
- ideconf |= u_clock << devid;
- pci_write_config_word(dev, 0x54, ideconf);
- } else {
- /* MWDMA is driven by the PIO timings. */
- it8213_set_timings(ap, adev, ata_mwdma_to_pio(speed), 1);
-
- udma_enable &= ~(1 << devid);
- }
- pci_write_config_byte(dev, 0x48, udma_enable);
-}
+#include "pata_it8213.h"
static struct scsi_host_template it8213_sht = {
ATA_BMDMA_SHT(DRV_NAME),
===================================================================
@@ -0,0 +1,150 @@
+
+/**
+ * it8213_cable_detect - check for 40/80 pin
+ * @ap: Port
+ *
+ * Perform cable detection for the 8213 ATA interface. This is
+ * different to the PIIX arrangement
+ */
+
+static int it8213_cable_detect(struct ata_port *ap)
+{
+ struct pci_dev *pdev = to_pci_dev(ap->host->dev);
+ u8 tmp;
+ pci_read_config_byte(pdev, 0x42, &tmp);
+ if (tmp & 2) /* The initial docs are incorrect */
+ return ATA_CBL_PATA40;
+ return ATA_CBL_PATA80;
+}
+
+static void it8213_set_timings(struct ata_port *ap, struct ata_device *adev,
+ u8 pio, bool use_mwdma)
+{
+ struct pci_dev *dev = to_pci_dev(ap->host->dev);
+ u8 master_port = ap->port_no ? 0x42 : 0x40;
+ u16 master_data;
+ int control = 0;
+
+ /*
+ * See Intel Document 298600-004 for the timing programing rules
+ * for PIIX/ICH. The 8213 is a clone so very similar
+ */
+
+ static const /* ISP RTC */
+ u8 timings[][2] = { { 0, 0 },
+ { 0, 0 },
+ { 1, 0 },
+ { 2, 1 },
+ { 2, 3 }, };
+
+ if (pio > 1 || use_mwdma)
+ control |= 1; /* TIME */
+ if (ata_pio_need_iordy(adev) || use_mwdma)
+ control |= 2; /* IE */
+ /* Bit 2 is set for ATAPI on the IT8213 - reverse of ICH/PIIX */
+ if (adev->class != ATA_DEV_ATA)
+ control |= 4; /* PPE */
+ /* If the drive MWDMA is faster than it can do PIO then
+ we must force PIO into PIO0 */
+ if (use_mwdma && adev->pio_mode < (XFER_PIO_0 + pio))
+ /* Enable DMA timing only */
+ control |= 8; /* PIO cycles in PIO0 */
+
+ pci_read_config_word(dev, master_port, &master_data);
+
+ /* Set PPE, IE, and TIME as appropriate */
+ if (adev->devno == 0) {
+ master_data &= 0xCCF0;
+ master_data |= control;
+ master_data |= (timings[pio][0] << 12) |
+ (timings[pio][1] << 8);
+ } else {
+ u8 slave_data;
+
+ master_data &= 0xFF0F;
+ master_data |= (control << 4);
+
+ /* Slave timing in separate register */
+ pci_read_config_byte(dev, 0x44, &slave_data);
+ slave_data &= 0xF0;
+ slave_data |= (timings[pio][0] << 2) | timings[pio][1];
+ pci_write_config_byte(dev, 0x44, slave_data);
+ }
+
+ master_data |= 0x4000; /* Ensure SITRE is set */
+ pci_write_config_word(dev, master_port, master_data);
+}
+
+/**
+ * it8213_set_piomode - Initialize host controller PATA PIO timings
+ * @ap: Port whose timings we are configuring
+ * @adev: Device whose timings we are configuring
+ *
+ * Set PIO mode for device, in host controller PCI config space.
+ *
+ * LOCKING:
+ * None (inherited from caller).
+ */
+
+static void it8213_set_piomode(struct ata_port *ap, struct ata_device *adev)
+{
+ it8213_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0, 0);
+}
+
+/**
+ * it8213_set_dmamode - Initialize host controller PATA DMA timings
+ * @ap: Port whose timings we are configuring
+ * @adev: Device to program
+ *
+ * Set UDMA/MWDMA mode for device, in host controller PCI config space.
+ * This device is basically an ICH alike.
+ *
+ * LOCKING:
+ * None (inherited from caller).
+ */
+
+static void it8213_set_dmamode(struct ata_port *ap, struct ata_device *adev)
+{
+ struct pci_dev *dev = to_pci_dev(ap->host->dev);
+ u8 speed = adev->dma_mode;
+ int devid = adev->devno;
+ u8 udma_enable;
+
+ pci_read_config_byte(dev, 0x48, &udma_enable);
+
+ if (speed >= XFER_UDMA_0) {
+ unsigned int udma = speed - XFER_UDMA_0;
+ u16 udma_timing;
+ u16 ideconf;
+ int u_clock, u_speed;
+
+ /* Clocks follow the PIIX style */
+ u_speed = min(2 - (udma & 1), udma);
+ if (udma > 4)
+ u_clock = 0x1000; /* 100Mhz */
+ else if (udma > 2)
+ u_clock = 1; /* 66Mhz */
+ else
+ u_clock = 0; /* 33Mhz */
+
+ udma_enable |= (1 << devid);
+
+ /* Load the UDMA cycle time */
+ pci_read_config_word(dev, 0x4A, &udma_timing);
+ udma_timing &= ~(3 << (4 * devid));
+ udma_timing |= u_speed << (4 * devid);
+ pci_write_config_word(dev, 0x4A, udma_timing);
+
+ /* Load the clock selection */
+ pci_read_config_word(dev, 0x54, &ideconf);
+ ideconf &= ~(0x1001 << devid);
+ ideconf |= u_clock << devid;
+ pci_write_config_word(dev, 0x54, ideconf);
+ } else {
+ /* MWDMA is driven by the PIO timings. */
+ it8213_set_timings(ap, adev, ata_mwdma_to_pio(speed), 1);
+
+ udma_enable &= ~(1 << devid);
+ }
+ pci_write_config_byte(dev, 0x48, udma_enable);
+}