Message ID | c47b72a38d5250634d016a2af4d6e9242231e9e3.1423551266.git.chen.fan.fnst@cn.fujitsu.com |
---|---|
State | New |
Headers | show |
diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c index 7ca077a..ece1487 100644 --- a/hw/pci/pcie_aer.c +++ b/hw/pci/pcie_aer.c @@ -123,7 +123,7 @@ int pcie_aer_init(PCIDevice *dev, uint16_t offset) PCI_ERR_UNC_SUPPORTED); pci_long_test_and_set_mask(dev->w1cmask + offset + PCI_ERR_COR_STATUS, - PCI_ERR_COR_STATUS); + PCI_ERR_COR_SUPPORTED); pci_set_long(dev->config + offset + PCI_ERR_COR_MASK, PCI_ERR_COR_MASK_DEFAULT);
From pcie spec, the bits attributes are RW1CS in Correctable Error Status Register, so this patch fix a wrong definition for PCI_ERR_COR_STATUS register with w1cmask type. Signed-off-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com> --- hw/pci/pcie_aer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)