| Message ID | 1423212497-11970-2-git-send-email-kishon@ti.com |
|---|---|
| State | Accepted |
| Delegated to: | Łukasz Majewski |
| Headers | show |
Hi Kishon, > Enabled clocks for dwc3 controller and USB PHY present in DRA7. > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > arch/arm/cpu/armv7/omap5/hw_data.c | 14 ++++++++++++++ > arch/arm/cpu/armv7/omap5/prcm-regs.c | 10 +++++----- > arch/arm/include/asm/omap_common.h | 4 ++-- > 3 files changed, 21 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c > b/arch/arm/cpu/armv7/omap5/hw_data.c index 95f1686..9315bce 100644 > --- a/arch/arm/cpu/armv7/omap5/hw_data.c > +++ b/arch/arm/cpu/armv7/omap5/hw_data.c > @@ -455,6 +455,10 @@ void enable_basic_clocks(void) > (*prcm)->cm_l4per_gpio6_clkctrl, > (*prcm)->cm_l4per_gpio7_clkctrl, > (*prcm)->cm_l4per_gpio8_clkctrl, > +#ifdef CONFIG_USB_DWC3 > + (*prcm)->cm_l3init_ocp2scp1_clkctrl, > + (*prcm)->cm_l3init_usb_otg_ss1_clkctrl, > +#endif > 0 > }; > > @@ -486,6 +490,16 @@ void enable_basic_clocks(void) > setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, > HSMMC_CLKCTRL_CLKSEL_MASK); > > +#ifdef CONFIG_USB_DWC3 > + /* Enable 960 MHz clock for dwc3 */ > + setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, > + OPTFCLKEN_REFCLK960M); > + > + /* Enable 32 KHz clock for dwc3 */ > + setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, > + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); > +#endif > + > /* Set the correct clock dividers for mmc */ > setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, > HSMMC_CLKCTRL_CLKSEL_DIV_MASK); > diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c > b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 0745d42..440bb40 100644 > --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c > +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c > @@ -575,7 +575,7 @@ struct prcm_regs const omap5_es2_prcm = { > .cm_div_m2_dpll_unipro = 0x4a0081d0, > .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, > .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, > - .cm_coreaon_usb_phy_core_clkctrl = 0x4A008640, > + .cm_coreaon_usb_phy1_core_clkctrl = 0x4A008640, > .cm_coreaon_bandgap_clkctrl = 0x4a008648, > .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, > > @@ -709,7 +709,7 @@ struct prcm_regs const omap5_es2_prcm = { > .cm_l3init_fsusb_clkctrl = 0x4a0096d0, > .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, > .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8, > - .cm_l3init_usb_otg_ss_clkctrl = 0x4a0096f0, > + .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0096f0, > > /* prm irqstatus regs */ > .prm_irqstatus_mpu_2 = 0x4ae06014, > @@ -801,8 +801,8 @@ struct prcm_regs const dra7xx_prcm = { > .cm_clkmode_dpll_dsp = 0x4a005234, > .cm_shadow_freq_config1 = 0x4a005260, > .cm_clkmode_dpll_gmac = 0x4a0052a8, > - .cm_coreaon_usb_phy_core_clkctrl = 0x4a008640, > - .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688, > + .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640, > + .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688, > > /* cm1.mpu */ > .cm_mpu_mpu_clkctrl = 0x4a005320, > @@ -908,7 +908,7 @@ struct prcm_regs const dra7xx_prcm = { > .cm_gmac_gmac_clkctrl = 0x4a0093d0, > .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, > .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, > - .cm_l3init_usb_otg_ss_clkctrl = 0x4a0093f0, > + .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0093f0, > > /* cm2.l4per */ > .cm_l4per_clkstctrl = 0x4a009700, > diff --git a/arch/arm/include/asm/omap_common.h > b/arch/arm/include/asm/omap_common.h index 323952f..bd43099 100644 > --- a/arch/arm/include/asm/omap_common.h > +++ b/arch/arm/include/asm/omap_common.h > @@ -143,7 +143,7 @@ struct prcm_regs { > u32 cm_div_m2_dpll_unipro; > u32 cm_ssc_deltamstep_dpll_unipro; > u32 cm_ssc_modfreqdiv_dpll_unipro; > - u32 cm_coreaon_usb_phy_core_clkctrl; > + u32 cm_coreaon_usb_phy1_core_clkctrl; > u32 cm_coreaon_usb_phy2_core_clkctrl; > > /* cm2.core */ > @@ -230,7 +230,7 @@ struct prcm_regs { > u32 cm_l3init_fsusb_clkctrl; > u32 cm_l3init_ocp2scp1_clkctrl; > u32 cm_l3init_ocp2scp3_clkctrl; > - u32 cm_l3init_usb_otg_ss_clkctrl; > + u32 cm_l3init_usb_otg_ss1_clkctrl; > > u32 prm_irqstatus_mpu_2; > Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 95f1686..9315bce 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -455,6 +455,10 @@ void enable_basic_clocks(void) (*prcm)->cm_l4per_gpio6_clkctrl, (*prcm)->cm_l4per_gpio7_clkctrl, (*prcm)->cm_l4per_gpio8_clkctrl, +#ifdef CONFIG_USB_DWC3 + (*prcm)->cm_l3init_ocp2scp1_clkctrl, + (*prcm)->cm_l3init_usb_otg_ss1_clkctrl, +#endif 0 }; @@ -486,6 +490,16 @@ void enable_basic_clocks(void) setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); +#ifdef CONFIG_USB_DWC3 + /* Enable 960 MHz clock for dwc3 */ + setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, + OPTFCLKEN_REFCLK960M); + + /* Enable 32 KHz clock for dwc3 */ + setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); +#endif + /* Set the correct clock dividers for mmc */ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, HSMMC_CLKCTRL_CLKSEL_DIV_MASK); diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 0745d42..440bb40 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -575,7 +575,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_div_m2_dpll_unipro = 0x4a0081d0, .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, - .cm_coreaon_usb_phy_core_clkctrl = 0x4A008640, + .cm_coreaon_usb_phy1_core_clkctrl = 0x4A008640, .cm_coreaon_bandgap_clkctrl = 0x4a008648, .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, @@ -709,7 +709,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_l3init_fsusb_clkctrl = 0x4a0096d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8, - .cm_l3init_usb_otg_ss_clkctrl = 0x4a0096f0, + .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0096f0, /* prm irqstatus regs */ .prm_irqstatus_mpu_2 = 0x4ae06014, @@ -801,8 +801,8 @@ struct prcm_regs const dra7xx_prcm = { .cm_clkmode_dpll_dsp = 0x4a005234, .cm_shadow_freq_config1 = 0x4a005260, .cm_clkmode_dpll_gmac = 0x4a0052a8, - .cm_coreaon_usb_phy_core_clkctrl = 0x4a008640, - .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688, + .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640, + .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688, /* cm1.mpu */ .cm_mpu_mpu_clkctrl = 0x4a005320, @@ -908,7 +908,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_gmac_gmac_clkctrl = 0x4a0093d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, - .cm_l3init_usb_otg_ss_clkctrl = 0x4a0093f0, + .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0093f0, /* cm2.l4per */ .cm_l4per_clkstctrl = 0x4a009700, diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 323952f..bd43099 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -143,7 +143,7 @@ struct prcm_regs { u32 cm_div_m2_dpll_unipro; u32 cm_ssc_deltamstep_dpll_unipro; u32 cm_ssc_modfreqdiv_dpll_unipro; - u32 cm_coreaon_usb_phy_core_clkctrl; + u32 cm_coreaon_usb_phy1_core_clkctrl; u32 cm_coreaon_usb_phy2_core_clkctrl; /* cm2.core */ @@ -230,7 +230,7 @@ struct prcm_regs { u32 cm_l3init_fsusb_clkctrl; u32 cm_l3init_ocp2scp1_clkctrl; u32 cm_l3init_ocp2scp3_clkctrl; - u32 cm_l3init_usb_otg_ss_clkctrl; + u32 cm_l3init_usb_otg_ss1_clkctrl; u32 prm_irqstatus_mpu_2;
Enabled clocks for dwc3 controller and USB PHY present in DRA7. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- arch/arm/cpu/armv7/omap5/hw_data.c | 14 ++++++++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 10 +++++----- arch/arm/include/asm/omap_common.h | 4 ++-- 3 files changed, 21 insertions(+), 7 deletions(-)