| Message ID | 20150206011714.2507.45712.stgit@tlendack-t1.amdoffice.net |
|---|---|
| State | Accepted, archived |
| Delegated to: | David Miller |
| Headers | show |
From: Tom Lendacky <thomas.lendacky@amd.com> Date: Thu, 5 Feb 2015 19:17:14 -0600 > When using per channel DMA interrupts the transmit interrupt (TI) and the > receive interrupt (RI) are masked off so as to not generate an interrupt > to the main ISR. However, should another interrupt fire for the DMA channel > that is handled by the main ISR the TI/RI bits can still be set. This > will cause the wrong and uninitialized napi structure to be used causing a > panic. Add a check to be sure per channel DMA interrupts are not enabled > before acting on those bit flags. > > Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Applied. -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c index e5ffb2c..477a7e3 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c @@ -337,12 +337,13 @@ static irqreturn_t xgbe_isr(int irq, void *data) dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); DBGPR(" DMA_CH%u_ISR = %08x\n", i, dma_ch_isr); - /* If we get a TI or RI interrupt that means per channel DMA - * interrupts are not enabled, so we use the private data napi - * structure, not the per channel napi structure + /* The TI or RI interrupt bits may still be set even if using + * per channel DMA interrupts. Check to be sure those are not + * enabled before using the private data napi structure. */ - if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) || - XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI)) { + if (!pdata->per_channel_irq && + (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) || + XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) { if (napi_schedule_prep(&pdata->napi)) { /* Disable Tx and Rx interrupts */ xgbe_disable_rx_tx_ints(pdata);
When using per channel DMA interrupts the transmit interrupt (TI) and the receive interrupt (RI) are masked off so as to not generate an interrupt to the main ISR. However, should another interrupt fire for the DMA channel that is handled by the main ISR the TI/RI bits can still be set. This will cause the wrong and uninitialized napi structure to be used causing a panic. Add a check to be sure per channel DMA interrupts are not enabled before acting on those bit flags. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> --- drivers/net/ethernet/amd/xgbe/xgbe-drv.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html