From patchwork Sat Jan 23 13:09:17 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [1/2] ARMv7: Initialize SCTLR on v7 so that it reads RAO bits as one. Date: Sat, 23 Jan 2010 03:09:17 -0000 From: Bahadir Balban X-Patchwork-Id: 43581 Message-Id: <1264252158-17262-1-git-send-email-bbalban@b-labs.co.uk> To: qemu-devel@nongnu.org Cc: Bahadir Balban If left uninitialized, read/update/write style access causes QEMU to interpret the architecture as non-v7 since bit 23 reads 0. Signed-off-by: Bahadir Balban --- target-arm/helper.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index b3aec99..0098053 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -101,6 +101,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100; memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t)); + env->cp15.c1_sys = (1 << 23) | (1 << 22) | (1 << 18) | (1 << 16) | (0xF << 3); env->cp15.c0_cachetype = 0x82048004; env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3; env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */ @@ -123,6 +124,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111; memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t)); + env->cp15.c1_sys = (1 << 23) | (1 << 22) | (1 << 18) | (1 << 16) | (0xF << 3); env->cp15.c0_cachetype = 0x80038003; env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3; env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */