[U-Boot,RFC,2/6] x86: quark: Add routines to access message bus registers

In the Quark SoC, some chipset commands are accomplished by utilizing
the internal message network within the host bridge (D0:F0). Accesses
to this network are accomplished by populating the message control
register (MCR), Message Control Register eXtension (MCRX) and the
message data register (MDR).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/quark/msg_port.c              | 76 ++++++++++++++++++++++++
 arch/x86/include/asm/arch-quark/msg_port.h | 93 ++++++++++++++++++++++++++++++
 2 files changed, 169 insertions(+)
 create mode 100644 arch/x86/cpu/quark/msg_port.c
 create mode 100644 arch/x86/include/asm/arch-quark/msg_port.h

Hi Bin,

On 28 January 2015 at 07:19, Bin Meng <bmeng.cn@gmail.com> wrote:
> In the Quark SoC, some chipset commands are accomplished by utilizing
> the internal message network within the host bridge (D0:F0). Accesses
> to this network are accomplished by populating the message control
> register (MCR), Message Control Register eXtension (MCRX) and the
> message data register (MDR).
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/quark/msg_port.c              | 76 ++++++++++++++++++++++++
>  arch/x86/include/asm/arch-quark/msg_port.h | 93 ++++++++++++++++++++++++++++++
>  2 files changed, 169 insertions(+)
>  create mode 100644 arch/x86/cpu/quark/msg_port.c
>  create mode 100644 arch/x86/include/asm/arch-quark/msg_port.h
>
> diff --git a/arch/x86/cpu/quark/msg_port.c b/arch/x86/cpu/quark/msg_port.c
> new file mode 100644
> index 0000000..a04462f
> --- /dev/null
> +++ b/arch/x86/cpu/quark/msg_port.c
> @@ -0,0 +1,76 @@
> +/*
> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <pci.h>
> +#include <asm/arch/device.h>
> +#include <asm/arch/msg_port.h>
> +
> +u32 msg_port_read(u8 port, u32 reg)
> +{
> +       u32 value;
> +
> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
> +                              reg & 0xffffff00);
> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
> +                              MCR_FILL(MSG_OP_READ, port, reg));
> +       pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
> +
> +       return value;

Interesting - so this uses PCI config space? Does writing to the
CTRL_REG actually cause anything to happen?

Could we remove the CTRL write with a function, like

void msg_port_setup(int op, int port, int reg)
{
      pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
         (((op) << 24) | ((port) << 16) | (((reg) << 8) & 0xff00) | 0xf0));
}

then we can remove MCR_FILL.

> +}
> +
> +void msg_port_write(u8 port, u32 reg, u32 value)
> +{
> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
> +                              reg & 0xffffff00);
> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
> +                              MCR_FILL(MSG_OP_WRITE, port, reg));
> +}
> +
> +u32 msg_port_alt_read(u8 port, u32 reg)
> +{
> +       u32 value;
> +
> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
> +                              reg & 0xffffff00);
> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
> +                              MCR_FILL(MSG_OP_ALT_READ, port, reg));
> +       pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
> +
> +       return value;
> +}
> +
> +void msg_port_alt_write(u8 port, u32 reg, u32 value)
> +{
> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
> +                              reg & 0xffffff00);
> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
> +                              MCR_FILL(MSG_OP_ALT_WRITE, port, reg));
> +}
> +
> +u32 msg_port_io_read(u8 port, u32 reg)
> +{
> +       u32 value;
> +
> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
> +                              reg & 0xffffff00);
> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
> +                              MCR_FILL(MSG_OP_IO_READ, port, reg));
> +       pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
> +
> +       return value;
> +}
> +
> +void msg_port_io_write(u8 port, u32 reg, u32 value)
> +{
> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
> +                              reg & 0xffffff00);
> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
> +                              MCR_FILL(MSG_OP_IO_WRITE, port, reg));
> +}
> diff --git a/arch/x86/include/asm/arch-quark/msg_port.h b/arch/x86/include/asm/arch-quark/msg_port.h
> new file mode 100644
> index 0000000..8f40adb
> --- /dev/null
> +++ b/arch/x86/include/asm/arch-quark/msg_port.h
> @@ -0,0 +1,93 @@
> +/*
> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#ifndef _QUARK_MSG_PORT_H_
> +#define _QUARK_MSG_PORT_H_
> +
> +/*
> + * In the Quark SoC, some chipset commands are accomplished by utilizing
> + * the internal message network within the host bridge (D0:F0). Accesses
> + * to this network are accomplished by populating the message control
> + * register (MCR), Message Control Register eXtension (MCRX) and the
> + * message data register (MDR).
> + */
> +#define MSG_CTRL_REG           0xD0    /* Message Control Register */
> +#define MSG_CTRL_EXT_REG       0xD4    /* Message Control Register EXT */
> +#define MSG_DATA_REG           0xD8    /* Message Data Register */
> +
> +/* Normal Read/Write OpCodes */
> +#define MSG_OP_READ            0x10
> +#define MSG_OP_WRITE           0x11
> +
> +/* Alternative Read/Write OpCodes */
> +#define MSG_OP_ALT_READ                0x06
> +#define MSG_OP_ALT_WRITE       0x07
> +
> +/* IO Read/Write OpCodes */
> +#define MSG_OP_IO_READ         0x02
> +#define MSG_OP_IO_WRITE                0x03
> +
> +#define MCR_FILL(op, port, reg)        \
> +       (((op) << 24) | ((port) << 16) | (((reg) << 8) & 0xff00) | 0xf0)
> +
> +/**
> + * msg_port_read - read a message port register using normal opcode
> + *
> + * @port:   port number on the message bus
> + * @reg:    register number within a port
> + *
> + * @return: message port register value
> + */
> +u32 msg_port_read(u8 port, u32 reg);
> +
> +/**
> + * msg_port_write - write a message port register using normal opcode
> + *
> + * @port:   port number on the message bus
> + * @reg:    register number within a port
> + * @value:  register value to write
> + */
> +void msg_port_write(u8 port, u32 reg, u32 value);
> +
> +/**
> + * msg_port_alt_read - read a message port register using alternative opcode
> + *
> + * @port:   port number on the message bus
> + * @reg:    register number within a port
> + *
> + * @return: message port register value
> + */
> +u32 msg_port_alt_read(u8 port, u32 reg);
> +
> +/**
> + * msg_port_alt_write - write a message port register using alternative opcode
> + *
> + * @port:   port number on the message bus
> + * @reg:    register number within a port
> + * @value:  register value to write
> + */
> +void msg_port_alt_write(u8 port, u32 reg, u32 value);
> +
> +/**
> + * msg_port_io_read - read a message port register using I/O opcode
> + *
> + * @port:   port number on the message bus
> + * @reg:    register number within a port
> + *
> + * @return: message port register value
> + */
> +u32 msg_port_io_read(u8 port, u32 reg);
> +
> +/**
> + * msg_port_io_write - write a message port register using I/O opcode
> + *
> + * @port:   port number on the message bus
> + * @reg:    register number within a port
> + * @value:  register value to write
> + */
> +void msg_port_io_write(u8 port, u32 reg, u32 value);
> +
> +#endif /* _QUARK_MSG_PORT_H_ */
> --
> 1.8.2.1
>

Regards,
Simon

Hi Simon,

On Thu, Jan 29, 2015 at 2:04 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 28 January 2015 at 07:19, Bin Meng <bmeng.cn@gmail.com> wrote:
>> In the Quark SoC, some chipset commands are accomplished by utilizing
>> the internal message network within the host bridge (D0:F0). Accesses
>> to this network are accomplished by populating the message control
>> register (MCR), Message Control Register eXtension (MCRX) and the
>> message data register (MDR).
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/quark/msg_port.c              | 76 ++++++++++++++++++++++++
>>  arch/x86/include/asm/arch-quark/msg_port.h | 93 ++++++++++++++++++++++++++++++
>>  2 files changed, 169 insertions(+)
>>  create mode 100644 arch/x86/cpu/quark/msg_port.c
>>  create mode 100644 arch/x86/include/asm/arch-quark/msg_port.h
>>
>> diff --git a/arch/x86/cpu/quark/msg_port.c b/arch/x86/cpu/quark/msg_port.c
>> new file mode 100644
>> index 0000000..a04462f
>> --- /dev/null
>> +++ b/arch/x86/cpu/quark/msg_port.c
>> @@ -0,0 +1,76 @@
>> +/*
>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
>> + *
>> + * SPDX-License-Identifier:    GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <pci.h>
>> +#include <asm/arch/device.h>
>> +#include <asm/arch/msg_port.h>
>> +
>> +u32 msg_port_read(u8 port, u32 reg)
>> +{
>> +       u32 value;
>> +
>> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
>> +                              reg & 0xffffff00);
>> +       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
>> +                              MCR_FILL(MSG_OP_READ, port, reg));
>> +       pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
>> +
>> +       return value;
>
> Interesting - so this uses PCI config space? Does writing to the
> CTRL_REG actually cause anything to happen?

The message port registers are indirectly accessed via 3 registers in
PCI configuration space, something like accessing PCI configuration
space register, but they are not within PCI configuration space. So
this is a two-level indirect access (first pci, then msg).

> Could we remove the CTRL write with a function, like
>
> void msg_port_setup(int op, int port, int reg)
> {
>       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
>          (((op) << 24) | ((port) << 16) | (((reg) << 8) & 0xff00) | 0xf0));
> }
>
> then we can remove MCR_FILL.
>

Yes.

[snip]

Regards,
Bin