diff mbox

[U-Boot,v2,22/22] x86: Add support for Intel Minnowboard Max

Message ID 1422422027-29599-23-git-send-email-sjg@chromium.org
State Accepted
Delegated to: Simon Glass
Headers show

Commit Message

Simon Glass Jan. 28, 2015, 5:13 a.m. UTC 
This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU. So far only the dual core 2GB variant is supported.

This uses the existing FSP support. Binary blobs are required to make this
board work. The microcode update is included as a patch (all 3000 lines of
it).

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Move CONFIG_SYS_CACHELINE_SIZE to the board CONFIG file
- Add comment about FSP setting PCIE_ECAM_BASE
- Put baytrail Kconfig in alphabetical order
- Remove superfluous check for CONFIG_DEBUG_UART in setup_early_uart()
- Fix compatible string for SPI flash
- Remove commented-out DEBUG_UART_CLOCK baud rate
- Rename 'Coreboot' to 'coreboot' in README.x86

 arch/x86/Kconfig                                 |   15 +
 arch/x86/cpu/Makefile                            |    1 +
 arch/x86/cpu/baytrail/Kconfig                    |    9 +
 arch/x86/cpu/baytrail/Makefile                   |   10 +
 arch/x86/cpu/baytrail/early_uart.c               |   78 +
 arch/x86/cpu/baytrail/fsp_configs.c              |  156 +
 arch/x86/cpu/baytrail/pci.c                      |   47 +
 arch/x86/cpu/baytrail/valleyview.c               |   38 +
 arch/x86/dts/Makefile                            |    3 +-
 arch/x86/dts/microcode/m0130673322.dtsi          | 3284 ++++++++++++++++++++++
 arch/x86/dts/minnowmax.dts                       |   45 +
 arch/x86/dts/serial.dtsi                         |    2 +-
 arch/x86/include/asm/arch-baytrail/fsp/azalia.h  |   39 +
 arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h |   95 +
 arch/x86/include/asm/arch-baytrail/gpio.h        |   13 +
 board/intel/minnowmax/Kconfig                    |   30 +
 board/intel/minnowmax/MAINTAINERS                |    6 +
 board/intel/minnowmax/Makefile                   |    7 +
 board/intel/minnowmax/minnowmax.c                |   32 +
 board/intel/minnowmax/start.S                    |    9 +
 configs/minnowmax_defconfig                      |   13 +
 doc/README.x86                                   |   47 +-
 include/configs/minnowmax.h                      |   72 +
 23 files changed, 4044 insertions(+), 7 deletions(-)
 create mode 100644 arch/x86/cpu/baytrail/Kconfig
 create mode 100644 arch/x86/cpu/baytrail/Makefile
 create mode 100644 arch/x86/cpu/baytrail/early_uart.c
 create mode 100644 arch/x86/cpu/baytrail/fsp_configs.c
 create mode 100644 arch/x86/cpu/baytrail/pci.c
 create mode 100644 arch/x86/cpu/baytrail/valleyview.c
 create mode 100644 arch/x86/dts/microcode/m0130673322.dtsi
 create mode 100644 arch/x86/dts/minnowmax.dts
 create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/azalia.h
 create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
 create mode 100644 arch/x86/include/asm/arch-baytrail/gpio.h
 create mode 100644 board/intel/minnowmax/Kconfig
 create mode 100644 board/intel/minnowmax/MAINTAINERS
 create mode 100644 board/intel/minnowmax/Makefile
 create mode 100644 board/intel/minnowmax/minnowmax.c
 create mode 100644 board/intel/minnowmax/start.S
 create mode 100644 configs/minnowmax_defconfig
 create mode 100644 include/configs/minnowmax.h

Comments

Bin Meng Jan. 28, 2015, 6:13 a.m. UTC | #1 
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass <sjg@chromium.org> wrote:
> This is a relatively low-cost x86 board in a small form factor. The main
> peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
> series CPU. So far only the dual core 2GB variant is supported.
>
> This uses the existing FSP support. Binary blobs are required to make this
> board work. The microcode update is included as a patch (all 3000 lines of
> it).
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Move CONFIG_SYS_CACHELINE_SIZE to the board CONFIG file
> - Add comment about FSP setting PCIE_ECAM_BASE
> - Put baytrail Kconfig in alphabetical order
> - Remove superfluous check for CONFIG_DEBUG_UART in setup_early_uart()
> - Fix compatible string for SPI flash
> - Remove commented-out DEBUG_UART_CLOCK baud rate
> - Rename 'Coreboot' to 'coreboot' in README.x86
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[snip]

Regards,
Bin
Simon Glass Jan. 28, 2015, 11:46 p.m. UTC | #2 
On 27 January 2015 at 22:13, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass <sjg@chromium.org> wrote:
>> This is a relatively low-cost x86 board in a small form factor. The main
>> peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
>> series CPU. So far only the dual core 2GB variant is supported.
>>
>> This uses the existing FSP support. Binary blobs are required to make this
>> board work. The microcode update is included as a patch (all 3000 lines of
>> it).
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2:
>> - Move CONFIG_SYS_CACHELINE_SIZE to the board CONFIG file
>> - Add comment about FSP setting PCIE_ECAM_BASE
>> - Put baytrail Kconfig in alphabetical order
>> - Remove superfluous check for CONFIG_DEBUG_UART in setup_early_uart()
>> - Fix compatible string for SPI flash
>> - Remove commented-out DEBUG_UART_CLOCK baud rate
>> - Rename 'Coreboot' to 'coreboot' in README.x86
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

(Rebased on top of upstream/master, so no longer has debug_uart and
this code was dropped for now)

Applied to u-boot-x86.
Andrew Bradford May 26, 2015, 7:52 p.m. UTC | #3 
Hi Simon and Bin (sorry for bringing this back from the dead),

But I have a question about fsp_configs.c down below:

On 01/27 22:13, Simon Glass wrote:
------------->8---------------
> diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
> new file mode 100644
> index 0000000..86b6926
> --- /dev/null
> +++ b/arch/x86/cpu/baytrail/fsp_configs.c
> @@ -0,0 +1,156 @@
> +/*
> + * Copyright (C) 2013, Intel Corporation
> + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
> + *
> + * SPDX-License-Identifier:	Intel
> + */
> +
> +#include <common.h>
> +#include <asm/arch/fsp/azalia.h>
> +#include <asm/fsp/fsp_support.h>
> +
> +/* ALC262 Verb Table - 10EC0262 */
> +static const uint32_t verb_table_data13[] = {
> +	/* Pin Complex (NID 0x11) */
> +	0x01171cf0,
> +	0x01171d11,
> +	0x01171e11,
> +	0x01171f41,
> +	/* Pin Complex (NID 0x12) */
> +	0x01271cf0,
> +	0x01271d11,
> +	0x01271e11,
> +	0x01271f41,
> +	/* Pin Complex (NID 0x14) */
> +	0x01471c10,
> +	0x01471d40,
> +	0x01471e01,
> +	0x01471f01,
> +	/* Pin Complex (NID 0x15) */
> +	0x01571cf0,
> +	0x01571d11,
> +	0x01571e11,
> +	0x01571f41,
> +	/* Pin Complex (NID 0x16) */
> +	0x01671cf0,
> +	0x01671d11,
> +	0x01671e11,
> +	0x01671f41,
> +	/* Pin Complex (NID 0x18) */
> +	0x01871c20,
> +	0x01871d98,
> +	0x01871ea1,
> +	0x01871f01,
> +	/* Pin Complex (NID 0x19) */
> +	0x01971c21,
> +	0x01971d98,
> +	0x01971ea1,
> +	0x01971f02,
> +	/* Pin Complex (NID 0x1A) */
> +	0x01a71c2f,
> +	0x01a71d30,
> +	0x01a71e81,
> +	0x01a71f01,
> +	/* Pin Complex */
> +	0x01b71c1f,
> +	0x01b71d40,
> +	0x01b71e21,
> +	0x01b71f02,
> +	/* Pin Complex */
> +	0x01c71cf0,
> +	0x01c71d11,
> +	0x01c71e11,
> +	0x01c71f41,
> +	/* Pin Complex */
> +	0x01d71c01,
> +	0x01d71dc6,
> +	0x01d71e14,
> +	0x01d71f40,
> +	/* Pin Complex */
> +	0x01e71cf0,
> +	0x01e71d11,
> +	0x01e71e11,
> +	0x01e71f41,
> +	/* Pin Complex */
> +	0x01f71cf0,
> +	0x01f71d11,
> +	0x01f71e11,
> +	0x01f71f41,
> +};
> +
> +/*
> + * This needs to be in ROM since if we put it in CAR, FSP init loses it when
> + * it drops CAR.
> + *
> + * TODO(sjg@chromium.org): Move to device tree when FSP allows it
> + *
> + * VerbTable: (RealTek ALC262)
> + * Revision ID = 0xFF, support all steps
> + * Codec Verb Table For AZALIA
> + * Codec Address: CAd value (0/1/2)
> + * Codec Vendor: 0x10EC0262
> + */
> +static const struct pch_azalia_verb_table azalia_verb_table[] = {
> +	{
> +		{
> +			0x10ec0262,
> +			0x0000,
> +			0xff,
> +			0x01,
> +			0x000b,
> +			0x0002,
> +		},
> +		verb_table_data13
> +	}
> +};
> +
> +const struct pch_azalia_config azalia_config = {
> +	.pme_enable = 1,
> +	.docking_supported = 1,
> +	.docking_attached = 0,
> +	.hdmi_codec_enable = 1,
> +	.azalia_v_ci_enable = 1,
> +	.rsvdbits = 0,
> +	.azalia_verb_table_num = 1,
> +	.azalia_verb_table = azalia_verb_table,
> +	.reset_wait_timer_us = 300
> +};
> +
> +void update_fsp_upd(struct upd_region *fsp_upd)
> +{
> +	struct memory_down_data *mem;
> +
> +	/*
> +	 * Configure everything here to avoid the poor hard-pressed user
> +	 * needing to run Intel's binary configuration tool. It may also allow
> +	 * us to support the 1GB single core variant easily.
> +	 *
> +	 * TODO(sjg@chromium.org): Move to device tree
> +	 */
> +	fsp_upd->mrc_init_tseg_size = 8;
> +	fsp_upd->mrc_init_mmio_size = 0x800;
> +	fsp_upd->emmc_boot_mode = 0xff;
> +	fsp_upd->enable_sdio = 1;
> +	fsp_upd->enable_sdcard = 1;
> +	fsp_upd->enable_hsuart0 = 1;
> +	fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
> +	fsp_upd->enable_i2_c0 = 0;
> +	fsp_upd->enable_i2_c2 = 0;
> +	fsp_upd->enable_i2_c3 = 0;
> +	fsp_upd->enable_i2_c4 = 0;
> +	fsp_upd->enable_xhci = 0;
> +	fsp_upd->igd_render_standby = 1;
> +
> +	mem = &fsp_upd->memory_params;
> +	mem->enable_memory_down = 1;
> +	mem->dram_speed = 1;
> +	mem->dimm_width = 1;
> +	mem->dimm_density = 2;
> +	mem->dimm_tcl = 0xb;
> +	mem->dimm_trpt_rcd = 0xb;
> +	mem->dimm_twr = 0xc;
> +	mem->dimm_twtr = 6;
> +	mem->dimm_trrd = 6;
> +	mem->dimm_trtp = 6;
> +	mem->dimm_tfaw = 0x14;
> +}

I am trying to move this fsp upd to use device tree as I am trying to
create a patch set to add the Intel Valley Island E38xx board (which
uses a SODIMM rather than memory down).  In doing so, I've found that
global data doesn't seem to be available when update_fsp_upd() is called
and generally it seems that gd->fdt_blob is used to get a reference to
the flattened device tree.

I'm not super familiar with device tree, but I was attempting to use
fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a
similar way that Quark does in my patchset (I've properly created the
COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts
file).  When I call fdtdec_next_compatible() the board does something
which I'm unable to debug (Valley Island does not have the early UART
pins connected so I have no early UART capability) but things just seem
to stop.

In manually tracing the calls which lead to update_fsp_upd(), it seems
that we haven't yet set up global data, so it makes sense that I can't
reference it.  But the device tree should be available in NOR flash or
in some other way which we can access in order to get the FSP UPD
settings.

Is there a simple way to access the device tree while it's still in NOR
flash so I can avoid using gd?  Or can global data be setup prior to
calling update_fsp_upd() (I believe we're still in CAR at this point)?
Or am I misunderstanding something basic here?

Did you have a rough outline of how this could be moved to device tree?

Thanks for your help!
-Andrew
Simon Glass May 26, 2015, 9:37 p.m. UTC | #4 
Hi Andrew,

On 26 May 2015 at 13:52, Andrew Bradford <andrew@bradfordembedded.com> wrote:
> Hi Simon and Bin (sorry for bringing this back from the dead),
>
> But I have a question about fsp_configs.c down below:
>
> On 01/27 22:13, Simon Glass wrote:
> ------------->8---------------
>> diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
>> new file mode 100644
>> index 0000000..86b6926
>> --- /dev/null
>> +++ b/arch/x86/cpu/baytrail/fsp_configs.c
>> @@ -0,0 +1,156 @@
>> +/*
>> + * Copyright (C) 2013, Intel Corporation
>> + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
>> + *
>> + * SPDX-License-Identifier:  Intel
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/arch/fsp/azalia.h>
>> +#include <asm/fsp/fsp_support.h>
>> +
>> +/* ALC262 Verb Table - 10EC0262 */
>> +static const uint32_t verb_table_data13[] = {
>> +     /* Pin Complex (NID 0x11) */
>> +     0x01171cf0,
>> +     0x01171d11,
>> +     0x01171e11,
>> +     0x01171f41,
>> +     /* Pin Complex (NID 0x12) */
>> +     0x01271cf0,
>> +     0x01271d11,
>> +     0x01271e11,
>> +     0x01271f41,
>> +     /* Pin Complex (NID 0x14) */
>> +     0x01471c10,
>> +     0x01471d40,
>> +     0x01471e01,
>> +     0x01471f01,
>> +     /* Pin Complex (NID 0x15) */
>> +     0x01571cf0,
>> +     0x01571d11,
>> +     0x01571e11,
>> +     0x01571f41,
>> +     /* Pin Complex (NID 0x16) */
>> +     0x01671cf0,
>> +     0x01671d11,
>> +     0x01671e11,
>> +     0x01671f41,
>> +     /* Pin Complex (NID 0x18) */
>> +     0x01871c20,
>> +     0x01871d98,
>> +     0x01871ea1,
>> +     0x01871f01,
>> +     /* Pin Complex (NID 0x19) */
>> +     0x01971c21,
>> +     0x01971d98,
>> +     0x01971ea1,
>> +     0x01971f02,
>> +     /* Pin Complex (NID 0x1A) */
>> +     0x01a71c2f,
>> +     0x01a71d30,
>> +     0x01a71e81,
>> +     0x01a71f01,
>> +     /* Pin Complex */
>> +     0x01b71c1f,
>> +     0x01b71d40,
>> +     0x01b71e21,
>> +     0x01b71f02,
>> +     /* Pin Complex */
>> +     0x01c71cf0,
>> +     0x01c71d11,
>> +     0x01c71e11,
>> +     0x01c71f41,
>> +     /* Pin Complex */
>> +     0x01d71c01,
>> +     0x01d71dc6,
>> +     0x01d71e14,
>> +     0x01d71f40,
>> +     /* Pin Complex */
>> +     0x01e71cf0,
>> +     0x01e71d11,
>> +     0x01e71e11,
>> +     0x01e71f41,
>> +     /* Pin Complex */
>> +     0x01f71cf0,
>> +     0x01f71d11,
>> +     0x01f71e11,
>> +     0x01f71f41,
>> +};
>> +
>> +/*
>> + * This needs to be in ROM since if we put it in CAR, FSP init loses it when
>> + * it drops CAR.
>> + *
>> + * TODO(sjg@chromium.org): Move to device tree when FSP allows it
>> + *
>> + * VerbTable: (RealTek ALC262)
>> + * Revision ID = 0xFF, support all steps
>> + * Codec Verb Table For AZALIA
>> + * Codec Address: CAd value (0/1/2)
>> + * Codec Vendor: 0x10EC0262
>> + */
>> +static const struct pch_azalia_verb_table azalia_verb_table[] = {
>> +     {
>> +             {
>> +                     0x10ec0262,
>> +                     0x0000,
>> +                     0xff,
>> +                     0x01,
>> +                     0x000b,
>> +                     0x0002,
>> +             },
>> +             verb_table_data13
>> +     }
>> +};
>> +
>> +const struct pch_azalia_config azalia_config = {
>> +     .pme_enable = 1,
>> +     .docking_supported = 1,
>> +     .docking_attached = 0,
>> +     .hdmi_codec_enable = 1,
>> +     .azalia_v_ci_enable = 1,
>> +     .rsvdbits = 0,
>> +     .azalia_verb_table_num = 1,
>> +     .azalia_verb_table = azalia_verb_table,
>> +     .reset_wait_timer_us = 300
>> +};
>> +
>> +void update_fsp_upd(struct upd_region *fsp_upd)
>> +{
>> +     struct memory_down_data *mem;
>> +
>> +     /*
>> +      * Configure everything here to avoid the poor hard-pressed user
>> +      * needing to run Intel's binary configuration tool. It may also allow
>> +      * us to support the 1GB single core variant easily.
>> +      *
>> +      * TODO(sjg@chromium.org): Move to device tree
>> +      */
>> +     fsp_upd->mrc_init_tseg_size = 8;
>> +     fsp_upd->mrc_init_mmio_size = 0x800;
>> +     fsp_upd->emmc_boot_mode = 0xff;
>> +     fsp_upd->enable_sdio = 1;
>> +     fsp_upd->enable_sdcard = 1;
>> +     fsp_upd->enable_hsuart0 = 1;
>> +     fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
>> +     fsp_upd->enable_i2_c0 = 0;
>> +     fsp_upd->enable_i2_c2 = 0;
>> +     fsp_upd->enable_i2_c3 = 0;
>> +     fsp_upd->enable_i2_c4 = 0;
>> +     fsp_upd->enable_xhci = 0;
>> +     fsp_upd->igd_render_standby = 1;
>> +
>> +     mem = &fsp_upd->memory_params;
>> +     mem->enable_memory_down = 1;
>> +     mem->dram_speed = 1;
>> +     mem->dimm_width = 1;
>> +     mem->dimm_density = 2;
>> +     mem->dimm_tcl = 0xb;
>> +     mem->dimm_trpt_rcd = 0xb;
>> +     mem->dimm_twr = 0xc;
>> +     mem->dimm_twtr = 6;
>> +     mem->dimm_trrd = 6;
>> +     mem->dimm_trtp = 6;
>> +     mem->dimm_tfaw = 0x14;
>> +}
>
> I am trying to move this fsp upd to use device tree as I am trying to
> create a patch set to add the Intel Valley Island E38xx board (which
> uses a SODIMM rather than memory down).  In doing so, I've found that
> global data doesn't seem to be available when update_fsp_upd() is called
> and generally it seems that gd->fdt_blob is used to get a reference to
> the flattened device tree.
>
> I'm not super familiar with device tree, but I was attempting to use
> fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a
> similar way that Quark does in my patchset (I've properly created the
> COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts
> file).  When I call fdtdec_next_compatible() the board does something
> which I'm unable to debug (Valley Island does not have the early UART
> pins connected so I have no early UART capability) but things just seem
> to stop.
>
> In manually tracing the calls which lead to update_fsp_upd(), it seems
> that we haven't yet set up global data, so it makes sense that I can't
> reference it.  But the device tree should be available in NOR flash or
> in some other way which we can access in order to get the FSP UPD
> settings.
>
> Is there a simple way to access the device tree while it's still in NOR
> flash so I can avoid using gd?  Or can global data be setup prior to
> calling update_fsp_upd() (I believe we're still in CAR at this point)?
> Or am I misunderstanding something basic here?
>
> Did you have a rough outline of how this could be moved to device tree?

This is a bit tricky. I would like to move fsp_init() later in the
init sequence (e.g. to board_init_f()). See this TODO in the code:

/*
* TODO:
*
* According to FSP architecture spec, the fsp_init() will not return
* to its caller, instead it requires the bootloader to provide a
* so-called continuation function to pass into the FSP as a parameter
* of fsp_init, and fsp_init() will call that continuation function
* directly.
*
* The call to fsp_init() may need to be moved out of the car_init()
* to cpu_init_f() with the help of some inline assembly codes.
* Note there is another issue that fsp_init() will setup another stack
* using the fsp_init parameter stack_top after DRAM is initialized,
* which means any data on the previous stack (on the CAR) gets lost
* (ie: U-Boot global_data). FSP is supposed to support such scenario,
* however it does not work. This should be revisited in the future.
*/

The primary issues are:
1. The need to recover the global_data
2. The need to change to a new stack

Re 1, my reading of the HOB stuff is that it is supposed to provide
you with a pointer to the CAR RAM (all ~128KB of it) so that you can
go back and find your old stack (and in our case, global_data).

Bin mentioned that this doesn't work - his is the comment above after
I asked him about it.

But if it could be made to work, then we could delay the init.

Re 2, U-Boot expects to change to a new stack when it wants to, which
is at the boundary of board_init_f() and board_init_r(). The Intel FSP
should not mandate a stack change over a C function call. IMO that is
just bad design. Dealing with it is not very easy, but one option is
to run with the new stack for the rest of the board_init_f() sequence
and then change stack again at the end of the sequence. Ick.

To specifically address your problem, global_data is not available
until board_init_f() is called, and the device tree comes into
existence soon after. We could hack around it - e.g. with microcode we
find it in the device tree and stick a pointer to it in a special
place. But the real solution is to figure out how to move this
fsp_init() stuff to later in the sequence. For non-FSP boards we don't
have this problem - e.g. ivybridge does RAM init long after we have
global_data and device tree. Note it is still running from flash at
this point, but CAR is set up and that is where global_data resides.

I'm interested to hear what you figure out.

>
> Thanks for your help!
> -Andrew

Regards,
Simon
Bin Meng May 27, 2015, 5:19 a.m. UTC | #5 
Hi Simon,

On Wed, May 27, 2015 at 5:37 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Andrew,
>
> On 26 May 2015 at 13:52, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>> Hi Simon and Bin (sorry for bringing this back from the dead),
>>
>> But I have a question about fsp_configs.c down below:
>>
>> On 01/27 22:13, Simon Glass wrote:
>> ------------->8---------------
>>> diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
>>> new file mode 100644
>>> index 0000000..86b6926
>>> --- /dev/null
>>> +++ b/arch/x86/cpu/baytrail/fsp_configs.c
>>> @@ -0,0 +1,156 @@
>>> +/*
>>> + * Copyright (C) 2013, Intel Corporation
>>> + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
>>> + *
>>> + * SPDX-License-Identifier:  Intel
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <asm/arch/fsp/azalia.h>
>>> +#include <asm/fsp/fsp_support.h>
>>> +
>>> +/* ALC262 Verb Table - 10EC0262 */
>>> +static const uint32_t verb_table_data13[] = {
>>> +     /* Pin Complex (NID 0x11) */
>>> +     0x01171cf0,
>>> +     0x01171d11,
>>> +     0x01171e11,
>>> +     0x01171f41,
>>> +     /* Pin Complex (NID 0x12) */
>>> +     0x01271cf0,
>>> +     0x01271d11,
>>> +     0x01271e11,
>>> +     0x01271f41,
>>> +     /* Pin Complex (NID 0x14) */
>>> +     0x01471c10,
>>> +     0x01471d40,
>>> +     0x01471e01,
>>> +     0x01471f01,
>>> +     /* Pin Complex (NID 0x15) */
>>> +     0x01571cf0,
>>> +     0x01571d11,
>>> +     0x01571e11,
>>> +     0x01571f41,
>>> +     /* Pin Complex (NID 0x16) */
>>> +     0x01671cf0,
>>> +     0x01671d11,
>>> +     0x01671e11,
>>> +     0x01671f41,
>>> +     /* Pin Complex (NID 0x18) */
>>> +     0x01871c20,
>>> +     0x01871d98,
>>> +     0x01871ea1,
>>> +     0x01871f01,
>>> +     /* Pin Complex (NID 0x19) */
>>> +     0x01971c21,
>>> +     0x01971d98,
>>> +     0x01971ea1,
>>> +     0x01971f02,
>>> +     /* Pin Complex (NID 0x1A) */
>>> +     0x01a71c2f,
>>> +     0x01a71d30,
>>> +     0x01a71e81,
>>> +     0x01a71f01,
>>> +     /* Pin Complex */
>>> +     0x01b71c1f,
>>> +     0x01b71d40,
>>> +     0x01b71e21,
>>> +     0x01b71f02,
>>> +     /* Pin Complex */
>>> +     0x01c71cf0,
>>> +     0x01c71d11,
>>> +     0x01c71e11,
>>> +     0x01c71f41,
>>> +     /* Pin Complex */
>>> +     0x01d71c01,
>>> +     0x01d71dc6,
>>> +     0x01d71e14,
>>> +     0x01d71f40,
>>> +     /* Pin Complex */
>>> +     0x01e71cf0,
>>> +     0x01e71d11,
>>> +     0x01e71e11,
>>> +     0x01e71f41,
>>> +     /* Pin Complex */
>>> +     0x01f71cf0,
>>> +     0x01f71d11,
>>> +     0x01f71e11,
>>> +     0x01f71f41,
>>> +};
>>> +
>>> +/*
>>> + * This needs to be in ROM since if we put it in CAR, FSP init loses it when
>>> + * it drops CAR.
>>> + *
>>> + * TODO(sjg@chromium.org): Move to device tree when FSP allows it
>>> + *
>>> + * VerbTable: (RealTek ALC262)
>>> + * Revision ID = 0xFF, support all steps
>>> + * Codec Verb Table For AZALIA
>>> + * Codec Address: CAd value (0/1/2)
>>> + * Codec Vendor: 0x10EC0262
>>> + */
>>> +static const struct pch_azalia_verb_table azalia_verb_table[] = {
>>> +     {
>>> +             {
>>> +                     0x10ec0262,
>>> +                     0x0000,
>>> +                     0xff,
>>> +                     0x01,
>>> +                     0x000b,
>>> +                     0x0002,
>>> +             },
>>> +             verb_table_data13
>>> +     }
>>> +};
>>> +
>>> +const struct pch_azalia_config azalia_config = {
>>> +     .pme_enable = 1,
>>> +     .docking_supported = 1,
>>> +     .docking_attached = 0,
>>> +     .hdmi_codec_enable = 1,
>>> +     .azalia_v_ci_enable = 1,
>>> +     .rsvdbits = 0,
>>> +     .azalia_verb_table_num = 1,
>>> +     .azalia_verb_table = azalia_verb_table,
>>> +     .reset_wait_timer_us = 300
>>> +};
>>> +
>>> +void update_fsp_upd(struct upd_region *fsp_upd)
>>> +{
>>> +     struct memory_down_data *mem;
>>> +
>>> +     /*
>>> +      * Configure everything here to avoid the poor hard-pressed user
>>> +      * needing to run Intel's binary configuration tool. It may also allow
>>> +      * us to support the 1GB single core variant easily.
>>> +      *
>>> +      * TODO(sjg@chromium.org): Move to device tree
>>> +      */
>>> +     fsp_upd->mrc_init_tseg_size = 8;
>>> +     fsp_upd->mrc_init_mmio_size = 0x800;
>>> +     fsp_upd->emmc_boot_mode = 0xff;
>>> +     fsp_upd->enable_sdio = 1;
>>> +     fsp_upd->enable_sdcard = 1;
>>> +     fsp_upd->enable_hsuart0 = 1;
>>> +     fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
>>> +     fsp_upd->enable_i2_c0 = 0;
>>> +     fsp_upd->enable_i2_c2 = 0;
>>> +     fsp_upd->enable_i2_c3 = 0;
>>> +     fsp_upd->enable_i2_c4 = 0;
>>> +     fsp_upd->enable_xhci = 0;
>>> +     fsp_upd->igd_render_standby = 1;
>>> +
>>> +     mem = &fsp_upd->memory_params;
>>> +     mem->enable_memory_down = 1;
>>> +     mem->dram_speed = 1;
>>> +     mem->dimm_width = 1;
>>> +     mem->dimm_density = 2;
>>> +     mem->dimm_tcl = 0xb;
>>> +     mem->dimm_trpt_rcd = 0xb;
>>> +     mem->dimm_twr = 0xc;
>>> +     mem->dimm_twtr = 6;
>>> +     mem->dimm_trrd = 6;
>>> +     mem->dimm_trtp = 6;
>>> +     mem->dimm_tfaw = 0x14;
>>> +}
>>
>> I am trying to move this fsp upd to use device tree as I am trying to
>> create a patch set to add the Intel Valley Island E38xx board (which
>> uses a SODIMM rather than memory down).  In doing so, I've found that
>> global data doesn't seem to be available when update_fsp_upd() is called
>> and generally it seems that gd->fdt_blob is used to get a reference to
>> the flattened device tree.
>>
>> I'm not super familiar with device tree, but I was attempting to use
>> fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a
>> similar way that Quark does in my patchset (I've properly created the
>> COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts
>> file).  When I call fdtdec_next_compatible() the board does something
>> which I'm unable to debug (Valley Island does not have the early UART
>> pins connected so I have no early UART capability) but things just seem
>> to stop.
>>
>> In manually tracing the calls which lead to update_fsp_upd(), it seems
>> that we haven't yet set up global data, so it makes sense that I can't
>> reference it.  But the device tree should be available in NOR flash or
>> in some other way which we can access in order to get the FSP UPD
>> settings.
>>
>> Is there a simple way to access the device tree while it's still in NOR
>> flash so I can avoid using gd?  Or can global data be setup prior to
>> calling update_fsp_upd() (I believe we're still in CAR at this point)?
>> Or am I misunderstanding something basic here?
>>
>> Did you have a rough outline of how this could be moved to device tree?
>
> This is a bit tricky. I would like to move fsp_init() later in the
> init sequence (e.g. to board_init_f()). See this TODO in the code:
>
> /*
> * TODO:
> *
> * According to FSP architecture spec, the fsp_init() will not return
> * to its caller, instead it requires the bootloader to provide a
> * so-called continuation function to pass into the FSP as a parameter
> * of fsp_init, and fsp_init() will call that continuation function
> * directly.
> *
> * The call to fsp_init() may need to be moved out of the car_init()
> * to cpu_init_f() with the help of some inline assembly codes.
> * Note there is another issue that fsp_init() will setup another stack
> * using the fsp_init parameter stack_top after DRAM is initialized,
> * which means any data on the previous stack (on the CAR) gets lost
> * (ie: U-Boot global_data). FSP is supposed to support such scenario,
> * however it does not work. This should be revisited in the future.
> */
>
> The primary issues are:
> 1. The need to recover the global_data
> 2. The need to change to a new stack
>
> Re 1, my reading of the HOB stuff is that it is supposed to provide
> you with a pointer to the CAR RAM (all ~128KB of it) so that you can
> go back and find your old stack (and in our case, global_data).
>
> Bin mentioned that this doesn't work - his is the comment above after
> I asked him about it.
>
> But if it could be made to work, then we could delay the init.
>
> Re 2, U-Boot expects to change to a new stack when it wants to, which
> is at the boundary of board_init_f() and board_init_r(). The Intel FSP
> should not mandate a stack change over a C function call. IMO that is
> just bad design. Dealing with it is not very easy, but one option is
> to run with the new stack for the rest of the board_init_f() sequence
> and then change stack again at the end of the sequence. Ick.
>
> To specifically address your problem, global_data is not available
> until board_init_f() is called, and the device tree comes into
> existence soon after. We could hack around it - e.g. with microcode we
> find it in the device tree and stick a pointer to it in a special
> place. But the real solution is to figure out how to move this
> fsp_init() stuff to later in the sequence. For non-FSP boards we don't
> have this problem - e.g. ivybridge does RAM init long after we have
> global_data and device tree. Note it is still running from flash at
> this point, but CAR is set up and that is where global_data resides.
>
> I'm interested to hear what you figure out.
>

I just noticed that Intel has released FSP specification v1.1 [1] in
April. After a rough read of the 1.1 spec, it looks to me that Intel
changed the fsp_init() design by breaking it down into 3 sub-routines:
FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might
be more logical to adapt U-Boot, but again I am not sure if the stack
migration stuff is still there. So far I don't see any new FSP
releases using the 1.1 spec.

[1] https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-architecture-spec-v1-1.html

Regards,
Bin
Andrew Bradford May 27, 2015, 2:22 p.m. UTC | #6 
Hi Simon & Bin,

On 05/26 15:37, Simon Glass wrote:
> Hi Andrew,
> 
> On 26 May 2015 at 13:52, Andrew Bradford <andrew@bradfordembedded.com> wrote:
> > Hi Simon and Bin (sorry for bringing this back from the dead),
> >
> > But I have a question about fsp_configs.c down below:
> >
> > On 01/27 22:13, Simon Glass wrote:
> > ------------->8---------------
> >> +void update_fsp_upd(struct upd_region *fsp_upd)
> >> +{
> >> +     struct memory_down_data *mem;
> >> +
> >> +     /*
> >> +      * Configure everything here to avoid the poor hard-pressed user
> >> +      * needing to run Intel's binary configuration tool. It may also allow
> >> +      * us to support the 1GB single core variant easily.
> >> +      *
> >> +      * TODO(sjg@chromium.org): Move to device tree
> >> +      */
> >> +     fsp_upd->mrc_init_tseg_size = 8;
> >> +     fsp_upd->mrc_init_mmio_size = 0x800;
> >> +     fsp_upd->emmc_boot_mode = 0xff;
> >> +     fsp_upd->enable_sdio = 1;
> >> +     fsp_upd->enable_sdcard = 1;
> >> +     fsp_upd->enable_hsuart0 = 1;
> >> +     fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
> >> +     fsp_upd->enable_i2_c0 = 0;
> >> +     fsp_upd->enable_i2_c2 = 0;
> >> +     fsp_upd->enable_i2_c3 = 0;
> >> +     fsp_upd->enable_i2_c4 = 0;
> >> +     fsp_upd->enable_xhci = 0;
> >> +     fsp_upd->igd_render_standby = 1;
> >> +
> >> +     mem = &fsp_upd->memory_params;
> >> +     mem->enable_memory_down = 1;
> >> +     mem->dram_speed = 1;
> >> +     mem->dimm_width = 1;
> >> +     mem->dimm_density = 2;
> >> +     mem->dimm_tcl = 0xb;
> >> +     mem->dimm_trpt_rcd = 0xb;
> >> +     mem->dimm_twr = 0xc;
> >> +     mem->dimm_twtr = 6;
> >> +     mem->dimm_trrd = 6;
> >> +     mem->dimm_trtp = 6;
> >> +     mem->dimm_tfaw = 0x14;
> >> +}
> >
> > I am trying to move this fsp upd to use device tree as I am trying to
> > create a patch set to add the Intel Valley Island E38xx board (which
> > uses a SODIMM rather than memory down).  In doing so, I've found that
> > global data doesn't seem to be available when update_fsp_upd() is called
> > and generally it seems that gd->fdt_blob is used to get a reference to
> > the flattened device tree.
> >
> > I'm not super familiar with device tree, but I was attempting to use
> > fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a
> > similar way that Quark does in my patchset (I've properly created the
> > COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts
> > file).  When I call fdtdec_next_compatible() the board does something
> > which I'm unable to debug (Valley Island does not have the early UART
> > pins connected so I have no early UART capability) but things just seem
> > to stop.
> >
> > In manually tracing the calls which lead to update_fsp_upd(), it seems
> > that we haven't yet set up global data, so it makes sense that I can't
> > reference it.  But the device tree should be available in NOR flash or
> > in some other way which we can access in order to get the FSP UPD
> > settings.
> >
> > Is there a simple way to access the device tree while it's still in NOR
> > flash so I can avoid using gd?  Or can global data be setup prior to
> > calling update_fsp_upd() (I believe we're still in CAR at this point)?
> > Or am I misunderstanding something basic here?
> >
> > Did you have a rough outline of how this could be moved to device tree?
> 
> This is a bit tricky. I would like to move fsp_init() later in the
> init sequence (e.g. to board_init_f()). See this TODO in the code:
> 
> /*
> * TODO:
> *
> * According to FSP architecture spec, the fsp_init() will not return
> * to its caller, instead it requires the bootloader to provide a
> * so-called continuation function to pass into the FSP as a parameter
> * of fsp_init, and fsp_init() will call that continuation function
> * directly.
> *
> * The call to fsp_init() may need to be moved out of the car_init()
> * to cpu_init_f() with the help of some inline assembly codes.
> * Note there is another issue that fsp_init() will setup another stack
> * using the fsp_init parameter stack_top after DRAM is initialized,
> * which means any data on the previous stack (on the CAR) gets lost
> * (ie: U-Boot global_data). FSP is supposed to support such scenario,
> * however it does not work. This should be revisited in the future.
> */
> 
> The primary issues are:
> 1. The need to recover the global_data
> 2. The need to change to a new stack
> 
> Re 1, my reading of the HOB stuff is that it is supposed to provide
> you with a pointer to the CAR RAM (all ~128KB of it) so that you can
> go back and find your old stack (and in our case, global_data).
> 
> Bin mentioned that this doesn't work - his is the comment above after
> I asked him about it.

OK, if it doesn't work then that's frustrating.

I do see that HOB 15 on my Valley Island board has the right GUID to be
the FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB and its size is 16408.  So that
has me hopeful, but likely I'll run into similar things that you two
have seen before.

Any pointers on why it was determined that the CAR RAM pointer doesn't
work correctly so I can avoid spending too much time investigating
things which have already been done?

> But if it could be made to work, then we could delay the init.
> 
> Re 2, U-Boot expects to change to a new stack when it wants to, which
> is at the boundary of board_init_f() and board_init_r(). The Intel FSP
> should not mandate a stack change over a C function call. IMO that is
> just bad design. Dealing with it is not very easy, but one option is
> to run with the new stack for the rest of the board_init_f() sequence
> and then change stack again at the end of the sequence. Ick.
> 
> To specifically address your problem, global_data is not available
> until board_init_f() is called, and the device tree comes into
> existence soon after. We could hack around it - e.g. with microcode we
> find it in the device tree and stick a pointer to it in a special
> place. But the real solution is to figure out how to move this
> fsp_init() stuff to later in the sequence. For non-FSP boards we don't
> have this problem - e.g. ivybridge does RAM init long after we have
> global_data and device tree. Note it is still running from flash at
> this point, but CAR is set up and that is where global_data resides.

Assuming that we can recover the CAR RAM data, would it make sense to
setup global data while in CAR so we can get access to the device tree
and then call fsp_init(), and once we're running from main memory just
set our global data pointer to the insides of the CAR RAM?

Likely I'm missing a few steps, here.  But this feels a lot like how SPL
works, except that u-boot is not in charge of how the relocation
happens, we're just along for the ride.

Thanks!
-Andrew
Andrew Bradford May 27, 2015, 2:39 p.m. UTC | #7 
On 05/27 13:19, Bin Meng wrote:
> Hi Simon,
> 
> On Wed, May 27, 2015 at 5:37 AM, Simon Glass <sjg@chromium.org> wrote:
> > Hi Andrew,
> >
> > On 26 May 2015 at 13:52, Andrew Bradford <andrew@bradfordembedded.com> wrote:
> >> Hi Simon and Bin (sorry for bringing this back from the dead),
> >>
> >> But I have a question about fsp_configs.c down below:
> >>
> >> On 01/27 22:13, Simon Glass wrote:
> >> ------------->8---------------
> >>> diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
> >>> new file mode 100644
> >>> index 0000000..86b6926
> >>> --- /dev/null
> >>> +++ b/arch/x86/cpu/baytrail/fsp_configs.c
> >>> @@ -0,0 +1,156 @@
> >>> +/*
> >>> + * Copyright (C) 2013, Intel Corporation
> >>> + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
> >>> + *
> >>> + * SPDX-License-Identifier:  Intel
> >>> + */
> >>> +
> >>> +#include <common.h>
> >>> +#include <asm/arch/fsp/azalia.h>
> >>> +#include <asm/fsp/fsp_support.h>
> >>> +
> >>> +/* ALC262 Verb Table - 10EC0262 */
> >>> +static const uint32_t verb_table_data13[] = {
> >>> +     /* Pin Complex (NID 0x11) */
> >>> +     0x01171cf0,
> >>> +     0x01171d11,
> >>> +     0x01171e11,
> >>> +     0x01171f41,
> >>> +     /* Pin Complex (NID 0x12) */
> >>> +     0x01271cf0,
> >>> +     0x01271d11,
> >>> +     0x01271e11,
> >>> +     0x01271f41,
> >>> +     /* Pin Complex (NID 0x14) */
> >>> +     0x01471c10,
> >>> +     0x01471d40,
> >>> +     0x01471e01,
> >>> +     0x01471f01,
> >>> +     /* Pin Complex (NID 0x15) */
> >>> +     0x01571cf0,
> >>> +     0x01571d11,
> >>> +     0x01571e11,
> >>> +     0x01571f41,
> >>> +     /* Pin Complex (NID 0x16) */
> >>> +     0x01671cf0,
> >>> +     0x01671d11,
> >>> +     0x01671e11,
> >>> +     0x01671f41,
> >>> +     /* Pin Complex (NID 0x18) */
> >>> +     0x01871c20,
> >>> +     0x01871d98,
> >>> +     0x01871ea1,
> >>> +     0x01871f01,
> >>> +     /* Pin Complex (NID 0x19) */
> >>> +     0x01971c21,
> >>> +     0x01971d98,
> >>> +     0x01971ea1,
> >>> +     0x01971f02,
> >>> +     /* Pin Complex (NID 0x1A) */
> >>> +     0x01a71c2f,
> >>> +     0x01a71d30,
> >>> +     0x01a71e81,
> >>> +     0x01a71f01,
> >>> +     /* Pin Complex */
> >>> +     0x01b71c1f,
> >>> +     0x01b71d40,
> >>> +     0x01b71e21,
> >>> +     0x01b71f02,
> >>> +     /* Pin Complex */
> >>> +     0x01c71cf0,
> >>> +     0x01c71d11,
> >>> +     0x01c71e11,
> >>> +     0x01c71f41,
> >>> +     /* Pin Complex */
> >>> +     0x01d71c01,
> >>> +     0x01d71dc6,
> >>> +     0x01d71e14,
> >>> +     0x01d71f40,
> >>> +     /* Pin Complex */
> >>> +     0x01e71cf0,
> >>> +     0x01e71d11,
> >>> +     0x01e71e11,
> >>> +     0x01e71f41,
> >>> +     /* Pin Complex */
> >>> +     0x01f71cf0,
> >>> +     0x01f71d11,
> >>> +     0x01f71e11,
> >>> +     0x01f71f41,
> >>> +};
> >>> +
> >>> +/*
> >>> + * This needs to be in ROM since if we put it in CAR, FSP init loses it when
> >>> + * it drops CAR.
> >>> + *
> >>> + * TODO(sjg@chromium.org): Move to device tree when FSP allows it
> >>> + *
> >>> + * VerbTable: (RealTek ALC262)
> >>> + * Revision ID = 0xFF, support all steps
> >>> + * Codec Verb Table For AZALIA
> >>> + * Codec Address: CAd value (0/1/2)
> >>> + * Codec Vendor: 0x10EC0262
> >>> + */
> >>> +static const struct pch_azalia_verb_table azalia_verb_table[] = {
> >>> +     {
> >>> +             {
> >>> +                     0x10ec0262,
> >>> +                     0x0000,
> >>> +                     0xff,
> >>> +                     0x01,
> >>> +                     0x000b,
> >>> +                     0x0002,
> >>> +             },
> >>> +             verb_table_data13
> >>> +     }
> >>> +};
> >>> +
> >>> +const struct pch_azalia_config azalia_config = {
> >>> +     .pme_enable = 1,
> >>> +     .docking_supported = 1,
> >>> +     .docking_attached = 0,
> >>> +     .hdmi_codec_enable = 1,
> >>> +     .azalia_v_ci_enable = 1,
> >>> +     .rsvdbits = 0,
> >>> +     .azalia_verb_table_num = 1,
> >>> +     .azalia_verb_table = azalia_verb_table,
> >>> +     .reset_wait_timer_us = 300
> >>> +};
> >>> +
> >>> +void update_fsp_upd(struct upd_region *fsp_upd)
> >>> +{
> >>> +     struct memory_down_data *mem;
> >>> +
> >>> +     /*
> >>> +      * Configure everything here to avoid the poor hard-pressed user
> >>> +      * needing to run Intel's binary configuration tool. It may also allow
> >>> +      * us to support the 1GB single core variant easily.
> >>> +      *
> >>> +      * TODO(sjg@chromium.org): Move to device tree
> >>> +      */
> >>> +     fsp_upd->mrc_init_tseg_size = 8;
> >>> +     fsp_upd->mrc_init_mmio_size = 0x800;
> >>> +     fsp_upd->emmc_boot_mode = 0xff;
> >>> +     fsp_upd->enable_sdio = 1;
> >>> +     fsp_upd->enable_sdcard = 1;
> >>> +     fsp_upd->enable_hsuart0 = 1;
> >>> +     fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
> >>> +     fsp_upd->enable_i2_c0 = 0;
> >>> +     fsp_upd->enable_i2_c2 = 0;
> >>> +     fsp_upd->enable_i2_c3 = 0;
> >>> +     fsp_upd->enable_i2_c4 = 0;
> >>> +     fsp_upd->enable_xhci = 0;
> >>> +     fsp_upd->igd_render_standby = 1;
> >>> +
> >>> +     mem = &fsp_upd->memory_params;
> >>> +     mem->enable_memory_down = 1;
> >>> +     mem->dram_speed = 1;
> >>> +     mem->dimm_width = 1;
> >>> +     mem->dimm_density = 2;
> >>> +     mem->dimm_tcl = 0xb;
> >>> +     mem->dimm_trpt_rcd = 0xb;
> >>> +     mem->dimm_twr = 0xc;
> >>> +     mem->dimm_twtr = 6;
> >>> +     mem->dimm_trrd = 6;
> >>> +     mem->dimm_trtp = 6;
> >>> +     mem->dimm_tfaw = 0x14;
> >>> +}
> >>
> >> I am trying to move this fsp upd to use device tree as I am trying to
> >> create a patch set to add the Intel Valley Island E38xx board (which
> >> uses a SODIMM rather than memory down).  In doing so, I've found that
> >> global data doesn't seem to be available when update_fsp_upd() is called
> >> and generally it seems that gd->fdt_blob is used to get a reference to
> >> the flattened device tree.
> >>
> >> I'm not super familiar with device tree, but I was attempting to use
> >> fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a
> >> similar way that Quark does in my patchset (I've properly created the
> >> COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts
> >> file).  When I call fdtdec_next_compatible() the board does something
> >> which I'm unable to debug (Valley Island does not have the early UART
> >> pins connected so I have no early UART capability) but things just seem
> >> to stop.
> >>
> >> In manually tracing the calls which lead to update_fsp_upd(), it seems
> >> that we haven't yet set up global data, so it makes sense that I can't
> >> reference it.  But the device tree should be available in NOR flash or
> >> in some other way which we can access in order to get the FSP UPD
> >> settings.
> >>
> >> Is there a simple way to access the device tree while it's still in NOR
> >> flash so I can avoid using gd?  Or can global data be setup prior to
> >> calling update_fsp_upd() (I believe we're still in CAR at this point)?
> >> Or am I misunderstanding something basic here?
> >>
> >> Did you have a rough outline of how this could be moved to device tree?
> >
> > This is a bit tricky. I would like to move fsp_init() later in the
> > init sequence (e.g. to board_init_f()). See this TODO in the code:
> >
> > /*
> > * TODO:
> > *
> > * According to FSP architecture spec, the fsp_init() will not return
> > * to its caller, instead it requires the bootloader to provide a
> > * so-called continuation function to pass into the FSP as a parameter
> > * of fsp_init, and fsp_init() will call that continuation function
> > * directly.
> > *
> > * The call to fsp_init() may need to be moved out of the car_init()
> > * to cpu_init_f() with the help of some inline assembly codes.
> > * Note there is another issue that fsp_init() will setup another stack
> > * using the fsp_init parameter stack_top after DRAM is initialized,
> > * which means any data on the previous stack (on the CAR) gets lost
> > * (ie: U-Boot global_data). FSP is supposed to support such scenario,
> > * however it does not work. This should be revisited in the future.
> > */
> >
> > The primary issues are:
> > 1. The need to recover the global_data
> > 2. The need to change to a new stack
> >
> > Re 1, my reading of the HOB stuff is that it is supposed to provide
> > you with a pointer to the CAR RAM (all ~128KB of it) so that you can
> > go back and find your old stack (and in our case, global_data).
> >
> > Bin mentioned that this doesn't work - his is the comment above after
> > I asked him about it.
> >
> > But if it could be made to work, then we could delay the init.
> >
> > Re 2, U-Boot expects to change to a new stack when it wants to, which
> > is at the boundary of board_init_f() and board_init_r(). The Intel FSP
> > should not mandate a stack change over a C function call. IMO that is
> > just bad design. Dealing with it is not very easy, but one option is
> > to run with the new stack for the rest of the board_init_f() sequence
> > and then change stack again at the end of the sequence. Ick.
> >
> > To specifically address your problem, global_data is not available
> > until board_init_f() is called, and the device tree comes into
> > existence soon after. We could hack around it - e.g. with microcode we
> > find it in the device tree and stick a pointer to it in a special
> > place. But the real solution is to figure out how to move this
> > fsp_init() stuff to later in the sequence. For non-FSP boards we don't
> > have this problem - e.g. ivybridge does RAM init long after we have
> > global_data and device tree. Note it is still running from flash at
> > this point, but CAR is set up and that is where global_data resides.
> >
> > I'm interested to hear what you figure out.
> >
> 
> I just noticed that Intel has released FSP specification v1.1 [1] in
> April. After a rough read of the 1.1 spec, it looks to me that Intel
> changed the fsp_init() design by breaking it down into 3 sub-routines:
> FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might
> be more logical to adapt U-Boot, but again I am not sure if the stack
> migration stuff is still there. So far I don't see any new FSP
> releases using the 1.1 spec.
> 
> [1] https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-architecture-spec-v1-1.html

There's also a very good overview of how to use an FSP v1.1 firmware at
[1].  It states that the problem in v1.0 for bootloaders was that when
you call FspInit() that temporary ram was torn down unconditionally.
Now, in v1.1, it says after calling FspMemoryInit() that control will be
given back to the bootloader running in the temporary ram (CAR?).  Then
the bootloader is responsible for migrating to main memory and to call
TempRamExit() so that temporary memory can be cleaned up.

This sounds like what u-boot would want and what Simon described above,
for u-boot to be in charge of relocating from CAR to main memory, right?
If so, likely things will be much easier once there's a v1.1 FSP for
baytrail...

[1]:http://firmware.intel.com/sites/default/files/resources/A_Tour_Beyond_BIOS_Creating_the_Intel_Firmware_Support_Package_Version_1_1_with_the_EFI_Developer_Kit_II.pdf

Thanks!
-Andrew
Simon Glass May 28, 2015, 4:20 p.m. UTC | #8 
Hi Bin,

On 26 May 2015 at 23:19, Bin Meng <bmeng.cn at gmail.com> wrote:
>
> Hi Simon,
>
> On Wed, May 27, 2015 at 5:37 AM, Simon Glass <sjg at chromium.org> wrote:
> > Hi Andrew,
> >
> > On 26 May 2015 at 13:52, Andrew Bradford <andrew at bradfordembedded.com> wrote:
> >> Hi Simon and Bin (sorry for bringing this back from the dead),
> >>
> >> But I have a question about fsp_configs.c down below:
> >>
> >> On 01/27 22:13, Simon Glass wrote:
> >> ------------->8---------------
[snip]

> >>> +
> >>> +const struct pch_azalia_config azalia_config = {
> >>> +     .pme_enable = 1,
> >>> +     .docking_supported = 1,
> >>> +     .docking_attached = 0,
> >>> +     .hdmi_codec_enable = 1,
> >>> +     .azalia_v_ci_enable = 1,
> >>> +     .rsvdbits = 0,
> >>> +     .azalia_verb_table_num = 1,
> >>> +     .azalia_verb_table = azalia_verb_table,
> >>> +     .reset_wait_timer_us = 300
> >>> +};
> >>> +
> >>> +void update_fsp_upd(struct upd_region *fsp_upd)
> >>> +{
> >>> +     struct memory_down_data *mem;
> >>> +
> >>> +     /*
> >>> +      * Configure everything here to avoid the poor hard-pressed user
> >>> +      * needing to run Intel's binary configuration tool. It may also allow
> >>> +      * us to support the 1GB single core variant easily.
> >>> +      *
> >>> +      * TODO(sjg at chromium.org): Move to device tree
> >>> +      */
> >>> +     fsp_upd->mrc_init_tseg_size = 8;
> >>> +     fsp_upd->mrc_init_mmio_size = 0x800;
> >>> +     fsp_upd->emmc_boot_mode = 0xff;
> >>> +     fsp_upd->enable_sdio = 1;
> >>> +     fsp_upd->enable_sdcard = 1;
> >>> +     fsp_upd->enable_hsuart0 = 1;
> >>> +     fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
> >>> +     fsp_upd->enable_i2_c0 = 0;
> >>> +     fsp_upd->enable_i2_c2 = 0;
> >>> +     fsp_upd->enable_i2_c3 = 0;
> >>> +     fsp_upd->enable_i2_c4 = 0;
> >>> +     fsp_upd->enable_xhci = 0;
> >>> +     fsp_upd->igd_render_standby = 1;
> >>> +
> >>> +     mem = &fsp_upd->memory_params;
> >>> +     mem->enable_memory_down = 1;
> >>> +     mem->dram_speed = 1;
> >>> +     mem->dimm_width = 1;
> >>> +     mem->dimm_density = 2;
> >>> +     mem->dimm_tcl = 0xb;
> >>> +     mem->dimm_trpt_rcd = 0xb;
> >>> +     mem->dimm_twr = 0xc;
> >>> +     mem->dimm_twtr = 6;
> >>> +     mem->dimm_trrd = 6;
> >>> +     mem->dimm_trtp = 6;
> >>> +     mem->dimm_tfaw = 0x14;
> >>> +}
> >>
> >> I am trying to move this fsp upd to use device tree as I am trying to
> >> create a patch set to add the Intel Valley Island E38xx board (which
> >> uses a SODIMM rather than memory down).  In doing so, I've found that
> >> global data doesn't seem to be available when update_fsp_upd() is called
> >> and generally it seems that gd->fdt_blob is used to get a reference to
> >> the flattened device tree.
> >>
> >> I'm not super familiar with device tree, but I was attempting to use
> >> fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a
> >> similar way that Quark does in my patchset (I've properly created the
> >> COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts
> >> file).  When I call fdtdec_next_compatible() the board does something
> >> which I'm unable to debug (Valley Island does not have the early UART
> >> pins connected so I have no early UART capability) but things just seem
> >> to stop.
> >>
> >> In manually tracing the calls which lead to update_fsp_upd(), it seems
> >> that we haven't yet set up global data, so it makes sense that I can't
> >> reference it.  But the device tree should be available in NOR flash or
> >> in some other way which we can access in order to get the FSP UPD
> >> settings.
> >>
> >> Is there a simple way to access the device tree while it's still in NOR
> >> flash so I can avoid using gd?  Or can global data be setup prior to
> >> calling update_fsp_upd() (I believe we're still in CAR at this point)?
> >> Or am I misunderstanding something basic here?
> >>
> >> Did you have a rough outline of how this could be moved to device tree?
> >
> > This is a bit tricky. I would like to move fsp_init() later in the
> > init sequence (e.g. to board_init_f()). See this TODO in the code:
> >
> > /*
> > * TODO:
> > *
> > * According to FSP architecture spec, the fsp_init() will not return
> > * to its caller, instead it requires the bootloader to provide a
> > * so-called continuation function to pass into the FSP as a parameter
> > * of fsp_init, and fsp_init() will call that continuation function
> > * directly.
> > *
> > * The call to fsp_init() may need to be moved out of the car_init()
> > * to cpu_init_f() with the help of some inline assembly codes.
> > * Note there is another issue that fsp_init() will setup another stack
> > * using the fsp_init parameter stack_top after DRAM is initialized,
> > * which means any data on the previous stack (on the CAR) gets lost
> > * (ie: U-Boot global_data). FSP is supposed to support such scenario,
> > * however it does not work. This should be revisited in the future.
> > */
> >
> > The primary issues are:
> > 1. The need to recover the global_data
> > 2. The need to change to a new stack
> >
> > Re 1, my reading of the HOB stuff is that it is supposed to provide
> > you with a pointer to the CAR RAM (all ~128KB of it) so that you can
> > go back and find your old stack (and in our case, global_data).
> >
> > Bin mentioned that this doesn't work - his is the comment above after
> > I asked him about it.
> >
> > But if it could be made to work, then we could delay the init.
> >
> > Re 2, U-Boot expects to change to a new stack when it wants to, which
> > is at the boundary of board_init_f() and board_init_r(). The Intel FSP
> > should not mandate a stack change over a C function call. IMO that is
> > just bad design. Dealing with it is not very easy, but one option is
> > to run with the new stack for the rest of the board_init_f() sequence
> > and then change stack again at the end of the sequence. Ick.
> >
> > To specifically address your problem, global_data is not available
> > until board_init_f() is called, and the device tree comes into
> > existence soon after. We could hack around it - e.g. with microcode we
> > find it in the device tree and stick a pointer to it in a special
> > place. But the real solution is to figure out how to move this
> > fsp_init() stuff to later in the sequence. For non-FSP boards we don't
> > have this problem - e.g. ivybridge does RAM init long after we have
> > global_data and device tree. Note it is still running from flash at
> > this point, but CAR is set up and that is where global_data resides.
> >
> > I'm interested to hear what you figure out.
> >
>
> I just noticed that Intel has released FSP specification v1.1 [1] in
> April. After a rough read of the 1.1 spec, it looks to me that Intel
> changed the fsp_init() design by breaking it down into 3 sub-routines:
> FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might
> be more logical to adapt U-Boot, but again I am not sure if the stack
> migration stuff is still there. So far I don't see any new FSP
> releases using the 1.1 spec.

Great! I sent an email with this feedback to Intel so perhaps they
took note. Although I suspect they would have got the same feedback
from any other firmware project. Once we see an FSP with this we
should be able to straighten this out. Hopefully they will update
Minnowmax. Even better if they decide to just release the source code.

>
> [1] https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-architecture-spec-v1-1.html
>
> Regards,
> Bin

Regards,
Simon
Simon Glass May 28, 2015, 4:29 p.m. UTC | #9 
Hi Andrew,

On 27 May 2015 at 08:22, Andrew Bradford <andrew at bradfordembedded.com> wrote:
> Hi Simon & Bin,
>
> On 05/26 15:37, Simon Glass wrote:
>> Hi Andrew,
>>
>> On 26 May 2015 at 13:52, Andrew Bradford <andrew at bradfordembedded.com> wrote:
>> > Hi Simon and Bin (sorry for bringing this back from the dead),
>> >
>> > But I have a question about fsp_configs.c down below:
>> >
>> > On 01/27 22:13, Simon Glass wrote:
>> > ------------->8---------------
>> >> +void update_fsp_upd(struct upd_region *fsp_upd)
>> >> +{
>> >> +     struct memory_down_data *mem;
>> >> +
>> >> +     /*
>> >> +      * Configure everything here to avoid the poor hard-pressed user
>> >> +      * needing to run Intel's binary configuration tool. It may also allow
>> >> +      * us to support the 1GB single core variant easily.
>> >> +      *
>> >> +      * TODO(sjg at chromium.org): Move to device tree
>> >> +      */
>> >> +     fsp_upd->mrc_init_tseg_size = 8;
>> >> +     fsp_upd->mrc_init_mmio_size = 0x800;
>> >> +     fsp_upd->emmc_boot_mode = 0xff;
>> >> +     fsp_upd->enable_sdio = 1;
>> >> +     fsp_upd->enable_sdcard = 1;
>> >> +     fsp_upd->enable_hsuart0 = 1;
>> >> +     fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
>> >> +     fsp_upd->enable_i2_c0 = 0;
>> >> +     fsp_upd->enable_i2_c2 = 0;
>> >> +     fsp_upd->enable_i2_c3 = 0;
>> >> +     fsp_upd->enable_i2_c4 = 0;
>> >> +     fsp_upd->enable_xhci = 0;
>> >> +     fsp_upd->igd_render_standby = 1;
>> >> +
>> >> +     mem = &fsp_upd->memory_params;
>> >> +     mem->enable_memory_down = 1;
>> >> +     mem->dram_speed = 1;
>> >> +     mem->dimm_width = 1;
>> >> +     mem->dimm_density = 2;
>> >> +     mem->dimm_tcl = 0xb;
>> >> +     mem->dimm_trpt_rcd = 0xb;
>> >> +     mem->dimm_twr = 0xc;
>> >> +     mem->dimm_twtr = 6;
>> >> +     mem->dimm_trrd = 6;
>> >> +     mem->dimm_trtp = 6;
>> >> +     mem->dimm_tfaw = 0x14;
>> >> +}
>> >
>> > I am trying to move this fsp upd to use device tree as I am trying to
>> > create a patch set to add the Intel Valley Island E38xx board (which
>> > uses a SODIMM rather than memory down).  In doing so, I've found that
>> > global data doesn't seem to be available when update_fsp_upd() is called
>> > and generally it seems that gd->fdt_blob is used to get a reference to
>> > the flattened device tree.
>> >
>> > I'm not super familiar with device tree, but I was attempting to use
>> > fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a
>> > similar way that Quark does in my patchset (I've properly created the
>> > COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts
>> > file).  When I call fdtdec_next_compatible() the board does something
>> > which I'm unable to debug (Valley Island does not have the early UART
>> > pins connected so I have no early UART capability) but things just seem
>> > to stop.
>> >
>> > In manually tracing the calls which lead to update_fsp_upd(), it seems
>> > that we haven't yet set up global data, so it makes sense that I can't
>> > reference it.  But the device tree should be available in NOR flash or
>> > in some other way which we can access in order to get the FSP UPD
>> > settings.
>> >
>> > Is there a simple way to access the device tree while it's still in NOR
>> > flash so I can avoid using gd?  Or can global data be setup prior to
>> > calling update_fsp_upd() (I believe we're still in CAR at this point)?
>> > Or am I misunderstanding something basic here?
>> >
>> > Did you have a rough outline of how this could be moved to device tree?
>>
>> This is a bit tricky. I would like to move fsp_init() later in the
>> init sequence (e.g. to board_init_f()). See this TODO in the code:
>>
>> /*
>> * TODO:
>> *
>> * According to FSP architecture spec, the fsp_init() will not return
>> * to its caller, instead it requires the bootloader to provide a
>> * so-called continuation function to pass into the FSP as a parameter
>> * of fsp_init, and fsp_init() will call that continuation function
>> * directly.
>> *
>> * The call to fsp_init() may need to be moved out of the car_init()
>> * to cpu_init_f() with the help of some inline assembly codes.
>> * Note there is another issue that fsp_init() will setup another stack
>> * using the fsp_init parameter stack_top after DRAM is initialized,
>> * which means any data on the previous stack (on the CAR) gets lost
>> * (ie: U-Boot global_data). FSP is supposed to support such scenario,
>> * however it does not work. This should be revisited in the future.
>> */
>>
>> The primary issues are:
>> 1. The need to recover the global_data
>> 2. The need to change to a new stack
>>
>> Re 1, my reading of the HOB stuff is that it is supposed to provide
>> you with a pointer to the CAR RAM (all ~128KB of it) so that you can
>> go back and find your old stack (and in our case, global_data).
>>
>> Bin mentioned that this doesn't work - his is the comment above after
>> I asked him about it.
>
> OK, if it doesn't work then that's frustrating.
>
> I do see that HOB 15 on my Valley Island board has the right GUID to be
> the FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB and its size is 16408.  So that
> has me hopeful, but likely I'll run into similar things that you two
> have seen before.

Well if you can get access to the old global_data here then you can
memcpy it to a new place in DRAM. That helps. But I forgot about issue
3:

3. Driver model will have created a few devices in temporary RAM and
now they are gone.

The easiest solution is to run the board_init_f() sequence again from
the start, this time skipping the dram init. It's horrible but pretty
easy to implement. So you end up running dram_init() twice. The first
time it runs the FSP call and then calls board_init_f() (or returns a
special value such that the sequence restarts). The second time it
does nothing.

Better might be to redo just the early malloc and driver model init:
initf_malloc() and initf_dm(). That might work.

>
> Any pointers on why it was determined that the CAR RAM pointer doesn't
> work correctly so I can avoid spending too much time investigating
> things which have already been done?
>
>> But if it could be made to work, then we could delay the init.
>>
>> Re 2, U-Boot expects to change to a new stack when it wants to, which
>> is at the boundary of board_init_f() and board_init_r(). The Intel FSP
>> should not mandate a stack change over a C function call. IMO that is
>> just bad design. Dealing with it is not very easy, but one option is
>> to run with the new stack for the rest of the board_init_f() sequence
>> and then change stack again at the end of the sequence. Ick.
>>
>> To specifically address your problem, global_data is not available
>> until board_init_f() is called, and the device tree comes into
>> existence soon after. We could hack around it - e.g. with microcode we
>> find it in the device tree and stick a pointer to it in a special
>> place. But the real solution is to figure out how to move this
>> fsp_init() stuff to later in the sequence. For non-FSP boards we don't
>> have this problem - e.g. ivybridge does RAM init long after we have
>> global_data and device tree. Note it is still running from flash at
>> this point, but CAR is set up and that is where global_data resides.
>
> Assuming that we can recover the CAR RAM data, would it make sense to
> setup global data while in CAR so we can get access to the device tree
> and then call fsp_init(), and once we're running from main memory just
> set our global data pointer to the insides of the CAR RAM?

CAR becomes unavailable when U-Boot relocates, since we want to use
the cache for actual caching rather than for RAM. Currently this
happens in init_cache_f_r() for non-FSP platforms, and it would be
great if Intel could fix it so that this happens for FSP platforms too
(as the link to the new FSP spec suggests).

>
> Likely I'm missing a few steps, here.  But this feels a lot like how SPL
> works, except that u-boot is not in charge of how the relocation
> happens, we're just along for the ride.

Exactly.

Note that the device tree is actually available very early - see the
fdtdec_setup() call which is one of the first things in the init
sequence. The problem is just how to move the FSP init into that
sequence, so that global_data is available.

Regards,
Simon
Simon Glass May 28, 2015, 4:30 p.m. UTC | #10 
Hi Andrew,

On 27 May 2015 at 08:39, Andrew Bradford <andrew at bradfordembedded.com> wrote:
> On 05/27 13:19, Bin Meng wrote:
>> Hi Simon,
>>
>> On Wed, May 27, 2015 at 5:37 AM, Simon Glass <sjg at chromium.org> wrote:
>> > Hi Andrew,
>> >
>> > On 26 May 2015 at 13:52, Andrew Bradford <andrew at bradfordembedded.com> wrote:
>> >> Hi Simon and Bin (sorry for bringing this back from the dead),
>> >>
>> >> But I have a question about fsp_configs.c down below:
>> >>
>> >> On 01/27 22:13, Simon Glass wrote:
>> >> ------------->8---------------
>> >>> diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
>> >>> new file mode 100644
>> >>> index 0000000..86b6926
>> >>> --- /dev/null
>> >>> +++ b/arch/x86/cpu/baytrail/fsp_configs.c
>> >>> @@ -0,0 +1,156 @@
>> >>> +/*
>> >>> + * Copyright (C) 2013, Intel Corporation
>> >>> + * Copyright (C) 2014, Bin Meng <bmeng.cn at gmail.com>
>> >>> + *
>> >>> + * SPDX-License-Identifier:  Intel
>> >>> + */
>> >>> +
>> >>> +#include <common.h>
>> >>> +#include <asm/arch/fsp/azalia.h>
>> >>> +#include <asm/fsp/fsp_support.h>
>> >>> +
>> >>> +/* ALC262 Verb Table - 10EC0262 */
>> >>> +static const uint32_t verb_table_data13[] = {
>> >>> +     /* Pin Complex (NID 0x11) */
>> >>> +     0x01171cf0,
>> >>> +     0x01171d11,
>> >>> +     0x01171e11,
>> >>> +     0x01171f41,
>> >>> +     /* Pin Complex (NID 0x12) */
>> >>> +     0x01271cf0,
>> >>> +     0x01271d11,
>> >>> +     0x01271e11,
>> >>> +     0x01271f41,
>> >>> +     /* Pin Complex (NID 0x14) */
>> >>> +     0x01471c10,
>> >>> +     0x01471d40,
>> >>> +     0x01471e01,
>> >>> +     0x01471f01,
>> >>> +     /* Pin Complex (NID 0x15) */
>> >>> +     0x01571cf0,
>> >>> +     0x01571d11,
>> >>> +     0x01571e11,
>> >>> +     0x01571f41,
>> >>> +     /* Pin Complex (NID 0x16) */
>> >>> +     0x01671cf0,
>> >>> +     0x01671d11,
>> >>> +     0x01671e11,
>> >>> +     0x01671f41,
>> >>> +     /* Pin Complex (NID 0x18) */
>> >>> +     0x01871c20,
>> >>> +     0x01871d98,
>> >>> +     0x01871ea1,
>> >>> +     0x01871f01,
>> >>> +     /* Pin Complex (NID 0x19) */
>> >>> +     0x01971c21,
>> >>> +     0x01971d98,
>> >>> +     0x01971ea1,
>> >>> +     0x01971f02,
>> >>> +     /* Pin Complex (NID 0x1A) */
>> >>> +     0x01a71c2f,
>> >>> +     0x01a71d30,
>> >>> +     0x01a71e81,
>> >>> +     0x01a71f01,
>> >>> +     /* Pin Complex */
>> >>> +     0x01b71c1f,
>> >>> +     0x01b71d40,
>> >>> +     0x01b71e21,
>> >>> +     0x01b71f02,
>> >>> +     /* Pin Complex */
>> >>> +     0x01c71cf0,
>> >>> +     0x01c71d11,
>> >>> +     0x01c71e11,
>> >>> +     0x01c71f41,
>> >>> +     /* Pin Complex */
>> >>> +     0x01d71c01,
>> >>> +     0x01d71dc6,
>> >>> +     0x01d71e14,
>> >>> +     0x01d71f40,
>> >>> +     /* Pin Complex */
>> >>> +     0x01e71cf0,
>> >>> +     0x01e71d11,
>> >>> +     0x01e71e11,
>> >>> +     0x01e71f41,
>> >>> +     /* Pin Complex */
>> >>> +     0x01f71cf0,
>> >>> +     0x01f71d11,
>> >>> +     0x01f71e11,
>> >>> +     0x01f71f41,
>> >>> +};
>> >>> +
>> >>> +/*
>> >>> + * This needs to be in ROM since if we put it in CAR, FSP init loses it when
>> >>> + * it drops CAR.
>> >>> + *
>> >>> + * TODO(sjg at chromium.org): Move to device tree when FSP allows it
>> >>> + *
>> >>> + * VerbTable: (RealTek ALC262)
>> >>> + * Revision ID = 0xFF, support all steps
>> >>> + * Codec Verb Table For AZALIA
>> >>> + * Codec Address: CAd value (0/1/2)
>> >>> + * Codec Vendor: 0x10EC0262
>> >>> + */
>> >>> +static const struct pch_azalia_verb_table azalia_verb_table[] = {
>> >>> +     {
>> >>> +             {
>> >>> +                     0x10ec0262,
>> >>> +                     0x0000,
>> >>> +                     0xff,
>> >>> +                     0x01,
>> >>> +                     0x000b,
>> >>> +                     0x0002,
>> >>> +             },
>> >>> +             verb_table_data13
>> >>> +     }
>> >>> +};
>> >>> +
>> >>> +const struct pch_azalia_config azalia_config = {
>> >>> +     .pme_enable = 1,
>> >>> +     .docking_supported = 1,
>> >>> +     .docking_attached = 0,
>> >>> +     .hdmi_codec_enable = 1,
>> >>> +     .azalia_v_ci_enable = 1,
>> >>> +     .rsvdbits = 0,
>> >>> +     .azalia_verb_table_num = 1,
>> >>> +     .azalia_verb_table = azalia_verb_table,
>> >>> +     .reset_wait_timer_us = 300
>> >>> +};
>> >>> +
>> >>> +void update_fsp_upd(struct upd_region *fsp_upd)
>> >>> +{
>> >>> +     struct memory_down_data *mem;
>> >>> +
>> >>> +     /*
>> >>> +      * Configure everything here to avoid the poor hard-pressed user
>> >>> +      * needing to run Intel's binary configuration tool. It may also allow
>> >>> +      * us to support the 1GB single core variant easily.
>> >>> +      *
>> >>> +      * TODO(sjg at chromium.org): Move to device tree
>> >>> +      */
>> >>> +     fsp_upd->mrc_init_tseg_size = 8;
>> >>> +     fsp_upd->mrc_init_mmio_size = 0x800;
>> >>> +     fsp_upd->emmc_boot_mode = 0xff;
>> >>> +     fsp_upd->enable_sdio = 1;
>> >>> +     fsp_upd->enable_sdcard = 1;
>> >>> +     fsp_upd->enable_hsuart0 = 1;
>> >>> +     fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
>> >>> +     fsp_upd->enable_i2_c0 = 0;
>> >>> +     fsp_upd->enable_i2_c2 = 0;
>> >>> +     fsp_upd->enable_i2_c3 = 0;
>> >>> +     fsp_upd->enable_i2_c4 = 0;
>> >>> +     fsp_upd->enable_xhci = 0;
>> >>> +     fsp_upd->igd_render_standby = 1;
>> >>> +
>> >>> +     mem = &fsp_upd->memory_params;
>> >>> +     mem->enable_memory_down = 1;
>> >>> +     mem->dram_speed = 1;
>> >>> +     mem->dimm_width = 1;
>> >>> +     mem->dimm_density = 2;
>> >>> +     mem->dimm_tcl = 0xb;
>> >>> +     mem->dimm_trpt_rcd = 0xb;
>> >>> +     mem->dimm_twr = 0xc;
>> >>> +     mem->dimm_twtr = 6;
>> >>> +     mem->dimm_trrd = 6;
>> >>> +     mem->dimm_trtp = 6;
>> >>> +     mem->dimm_tfaw = 0x14;
>> >>> +}
>> >>
>> >> I am trying to move this fsp upd to use device tree as I am trying to
>> >> create a patch set to add the Intel Valley Island E38xx board (which
>> >> uses a SODIMM rather than memory down).  In doing so, I've found that
>> >> global data doesn't seem to be available when update_fsp_upd() is called
>> >> and generally it seems that gd->fdt_blob is used to get a reference to
>> >> the flattened device tree.
>> >>
>> >> I'm not super familiar with device tree, but I was attempting to use
>> >> fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a
>> >> similar way that Quark does in my patchset (I've properly created the
>> >> COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts
>> >> file).  When I call fdtdec_next_compatible() the board does something
>> >> which I'm unable to debug (Valley Island does not have the early UART
>> >> pins connected so I have no early UART capability) but things just seem
>> >> to stop.
>> >>
>> >> In manually tracing the calls which lead to update_fsp_upd(), it seems
>> >> that we haven't yet set up global data, so it makes sense that I can't
>> >> reference it.  But the device tree should be available in NOR flash or
>> >> in some other way which we can access in order to get the FSP UPD
>> >> settings.
>> >>
>> >> Is there a simple way to access the device tree while it's still in NOR
>> >> flash so I can avoid using gd?  Or can global data be setup prior to
>> >> calling update_fsp_upd() (I believe we're still in CAR at this point)?
>> >> Or am I misunderstanding something basic here?
>> >>
>> >> Did you have a rough outline of how this could be moved to device tree?
>> >
>> > This is a bit tricky. I would like to move fsp_init() later in the
>> > init sequence (e.g. to board_init_f()). See this TODO in the code:
>> >
>> > /*
>> > * TODO:
>> > *
>> > * According to FSP architecture spec, the fsp_init() will not return
>> > * to its caller, instead it requires the bootloader to provide a
>> > * so-called continuation function to pass into the FSP as a parameter
>> > * of fsp_init, and fsp_init() will call that continuation function
>> > * directly.
>> > *
>> > * The call to fsp_init() may need to be moved out of the car_init()
>> > * to cpu_init_f() with the help of some inline assembly codes.
>> > * Note there is another issue that fsp_init() will setup another stack
>> > * using the fsp_init parameter stack_top after DRAM is initialized,
>> > * which means any data on the previous stack (on the CAR) gets lost
>> > * (ie: U-Boot global_data). FSP is supposed to support such scenario,
>> > * however it does not work. This should be revisited in the future.
>> > */
>> >
>> > The primary issues are:
>> > 1. The need to recover the global_data
>> > 2. The need to change to a new stack
>> >
>> > Re 1, my reading of the HOB stuff is that it is supposed to provide
>> > you with a pointer to the CAR RAM (all ~128KB of it) so that you can
>> > go back and find your old stack (and in our case, global_data).
>> >
>> > Bin mentioned that this doesn't work - his is the comment above after
>> > I asked him about it.
>> >
>> > But if it could be made to work, then we could delay the init.
>> >
>> > Re 2, U-Boot expects to change to a new stack when it wants to, which
>> > is at the boundary of board_init_f() and board_init_r(). The Intel FSP
>> > should not mandate a stack change over a C function call. IMO that is
>> > just bad design. Dealing with it is not very easy, but one option is
>> > to run with the new stack for the rest of the board_init_f() sequence
>> > and then change stack again at the end of the sequence. Ick.
>> >
>> > To specifically address your problem, global_data is not available
>> > until board_init_f() is called, and the device tree comes into
>> > existence soon after. We could hack around it - e.g. with microcode we
>> > find it in the device tree and stick a pointer to it in a special
>> > place. But the real solution is to figure out how to move this
>> > fsp_init() stuff to later in the sequence. For non-FSP boards we don't
>> > have this problem - e.g. ivybridge does RAM init long after we have
>> > global_data and device tree. Note it is still running from flash at
>> > this point, but CAR is set up and that is where global_data resides.
>> >
>> > I'm interested to hear what you figure out.
>> >
>>
>> I just noticed that Intel has released FSP specification v1.1 [1] in
>> April. After a rough read of the 1.1 spec, it looks to me that Intel
>> changed the fsp_init() design by breaking it down into 3 sub-routines:
>> FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might
>> be more logical to adapt U-Boot, but again I am not sure if the stack
>> migration stuff is still there. So far I don't see any new FSP
>> releases using the 1.1 spec.
>>
>> [1] https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-architecture-spec-v1-1.html
>
> There's also a very good overview of how to use an FSP v1.1 firmware at
> [1].  It states that the problem in v1.0 for bootloaders was that when
> you call FspInit() that temporary ram was torn down unconditionally.
> Now, in v1.1, it says after calling FspMemoryInit() that control will be
> given back to the bootloader running in the temporary ram (CAR?).  Then
> the bootloader is responsible for migrating to main memory and to call
> TempRamExit() so that temporary memory can be cleaned up.
>
> This sounds like what u-boot would want and what Simon described above,
> for u-boot to be in charge of relocating from CAR to main memory, right?
> If so, likely things will be much easier once there's a v1.1 FSP for
> baytrail...
>

Indeed, care to ping them to find out when this might happen?

> [1]:http://firmware.intel.com/sites/default/files/resources/A_Tour_Beyond_BIOS_Creating_the_Intel_Firmware_Support_Package_Version_1_1_with_the_EFI_Developer_Kit_II.pdf
>
> Thanks!
> -Andrew

Regards,
Simon
Andrew Bradford May 28, 2015, 6:09 p.m. UTC | #11 
On 05/28 10:30, Simon Glass wrote:
> Hi Andrew,
> 
> On 27 May 2015 at 08:39, Andrew Bradford <andrew at bradfordembedded.com> wrote:
> > On 05/27 13:19, Bin Meng wrote:
> >> Hi Simon,
> >>
> >> On Wed, May 27, 2015 at 5:37 AM, Simon Glass <sjg at chromium.org> wrote:
> >> > Hi Andrew,
> >> >
> >> > On 26 May 2015 at 13:52, Andrew Bradford <andrew at bradfordembedded.com> wrote:
> >> >> Hi Simon and Bin (sorry for bringing this back from the dead),
> >> >>
> >> >> But I have a question about fsp_configs.c down below:
> >> >>
> >> >> On 01/27 22:13, Simon Glass wrote:
> >> >> ------------->8---------------
> >> >>> diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
> >> >>> new file mode 100644
> >> >>> index 0000000..86b6926
> >> >>> --- /dev/null
> >> >>> +++ b/arch/x86/cpu/baytrail/fsp_configs.c
> >> >>> @@ -0,0 +1,156 @@
> >> >>> +/*
> >> >>> + * Copyright (C) 2013, Intel Corporation
> >> >>> + * Copyright (C) 2014, Bin Meng <bmeng.cn at gmail.com>
> >> >>> + *
> >> >>> + * SPDX-License-Identifier:  Intel
> >> >>> + */
> >> >>> +
> >> >>> +#include <common.h>
> >> >>> +#include <asm/arch/fsp/azalia.h>
> >> >>> +#include <asm/fsp/fsp_support.h>
> >> >>> +
> >> >>> +/* ALC262 Verb Table - 10EC0262 */
> >> >>> +static const uint32_t verb_table_data13[] = {
> >> >>> +     /* Pin Complex (NID 0x11) */
> >> >>> +     0x01171cf0,
> >> >>> +     0x01171d11,
> >> >>> +     0x01171e11,
> >> >>> +     0x01171f41,
> >> >>> +     /* Pin Complex (NID 0x12) */
> >> >>> +     0x01271cf0,
> >> >>> +     0x01271d11,
> >> >>> +     0x01271e11,
> >> >>> +     0x01271f41,
> >> >>> +     /* Pin Complex (NID 0x14) */
> >> >>> +     0x01471c10,
> >> >>> +     0x01471d40,
> >> >>> +     0x01471e01,
> >> >>> +     0x01471f01,
> >> >>> +     /* Pin Complex (NID 0x15) */
> >> >>> +     0x01571cf0,
> >> >>> +     0x01571d11,
> >> >>> +     0x01571e11,
> >> >>> +     0x01571f41,
> >> >>> +     /* Pin Complex (NID 0x16) */
> >> >>> +     0x01671cf0,
> >> >>> +     0x01671d11,
> >> >>> +     0x01671e11,
> >> >>> +     0x01671f41,
> >> >>> +     /* Pin Complex (NID 0x18) */
> >> >>> +     0x01871c20,
> >> >>> +     0x01871d98,
> >> >>> +     0x01871ea1,
> >> >>> +     0x01871f01,
> >> >>> +     /* Pin Complex (NID 0x19) */
> >> >>> +     0x01971c21,
> >> >>> +     0x01971d98,
> >> >>> +     0x01971ea1,
> >> >>> +     0x01971f02,
> >> >>> +     /* Pin Complex (NID 0x1A) */
> >> >>> +     0x01a71c2f,
> >> >>> +     0x01a71d30,
> >> >>> +     0x01a71e81,
> >> >>> +     0x01a71f01,
> >> >>> +     /* Pin Complex */
> >> >>> +     0x01b71c1f,
> >> >>> +     0x01b71d40,
> >> >>> +     0x01b71e21,
> >> >>> +     0x01b71f02,
> >> >>> +     /* Pin Complex */
> >> >>> +     0x01c71cf0,
> >> >>> +     0x01c71d11,
> >> >>> +     0x01c71e11,
> >> >>> +     0x01c71f41,
> >> >>> +     /* Pin Complex */
> >> >>> +     0x01d71c01,
> >> >>> +     0x01d71dc6,
> >> >>> +     0x01d71e14,
> >> >>> +     0x01d71f40,
> >> >>> +     /* Pin Complex */
> >> >>> +     0x01e71cf0,
> >> >>> +     0x01e71d11,
> >> >>> +     0x01e71e11,
> >> >>> +     0x01e71f41,
> >> >>> +     /* Pin Complex */
> >> >>> +     0x01f71cf0,
> >> >>> +     0x01f71d11,
> >> >>> +     0x01f71e11,
> >> >>> +     0x01f71f41,
> >> >>> +};
> >> >>> +
> >> >>> +/*
> >> >>> + * This needs to be in ROM since if we put it in CAR, FSP init loses it when
> >> >>> + * it drops CAR.
> >> >>> + *
> >> >>> + * TODO(sjg at chromium.org): Move to device tree when FSP allows it
> >> >>> + *
> >> >>> + * VerbTable: (RealTek ALC262)
> >> >>> + * Revision ID = 0xFF, support all steps
> >> >>> + * Codec Verb Table For AZALIA
> >> >>> + * Codec Address: CAd value (0/1/2)
> >> >>> + * Codec Vendor: 0x10EC0262
> >> >>> + */
> >> >>> +static const struct pch_azalia_verb_table azalia_verb_table[] = {
> >> >>> +     {
> >> >>> +             {
> >> >>> +                     0x10ec0262,
> >> >>> +                     0x0000,
> >> >>> +                     0xff,
> >> >>> +                     0x01,
> >> >>> +                     0x000b,
> >> >>> +                     0x0002,
> >> >>> +             },
> >> >>> +             verb_table_data13
> >> >>> +     }
> >> >>> +};
> >> >>> +
> >> >>> +const struct pch_azalia_config azalia_config = {
> >> >>> +     .pme_enable = 1,
> >> >>> +     .docking_supported = 1,
> >> >>> +     .docking_attached = 0,
> >> >>> +     .hdmi_codec_enable = 1,
> >> >>> +     .azalia_v_ci_enable = 1,
> >> >>> +     .rsvdbits = 0,
> >> >>> +     .azalia_verb_table_num = 1,
> >> >>> +     .azalia_verb_table = azalia_verb_table,
> >> >>> +     .reset_wait_timer_us = 300
> >> >>> +};
> >> >>> +
> >> >>> +void update_fsp_upd(struct upd_region *fsp_upd)
> >> >>> +{
> >> >>> +     struct memory_down_data *mem;
> >> >>> +
> >> >>> +     /*
> >> >>> +      * Configure everything here to avoid the poor hard-pressed user
> >> >>> +      * needing to run Intel's binary configuration tool. It may also allow
> >> >>> +      * us to support the 1GB single core variant easily.
> >> >>> +      *
> >> >>> +      * TODO(sjg at chromium.org): Move to device tree
> >> >>> +      */
> >> >>> +     fsp_upd->mrc_init_tseg_size = 8;
> >> >>> +     fsp_upd->mrc_init_mmio_size = 0x800;
> >> >>> +     fsp_upd->emmc_boot_mode = 0xff;
> >> >>> +     fsp_upd->enable_sdio = 1;
> >> >>> +     fsp_upd->enable_sdcard = 1;
> >> >>> +     fsp_upd->enable_hsuart0 = 1;
> >> >>> +     fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
> >> >>> +     fsp_upd->enable_i2_c0 = 0;
> >> >>> +     fsp_upd->enable_i2_c2 = 0;
> >> >>> +     fsp_upd->enable_i2_c3 = 0;
> >> >>> +     fsp_upd->enable_i2_c4 = 0;
> >> >>> +     fsp_upd->enable_xhci = 0;
> >> >>> +     fsp_upd->igd_render_standby = 1;
> >> >>> +
> >> >>> +     mem = &fsp_upd->memory_params;
> >> >>> +     mem->enable_memory_down = 1;
> >> >>> +     mem->dram_speed = 1;
> >> >>> +     mem->dimm_width = 1;
> >> >>> +     mem->dimm_density = 2;
> >> >>> +     mem->dimm_tcl = 0xb;
> >> >>> +     mem->dimm_trpt_rcd = 0xb;
> >> >>> +     mem->dimm_twr = 0xc;
> >> >>> +     mem->dimm_twtr = 6;
> >> >>> +     mem->dimm_trrd = 6;
> >> >>> +     mem->dimm_trtp = 6;
> >> >>> +     mem->dimm_tfaw = 0x14;
> >> >>> +}
> >> >>
> >> >> I am trying to move this fsp upd to use device tree as I am trying to
> >> >> create a patch set to add the Intel Valley Island E38xx board (which
> >> >> uses a SODIMM rather than memory down).  In doing so, I've found that
> >> >> global data doesn't seem to be available when update_fsp_upd() is called
> >> >> and generally it seems that gd->fdt_blob is used to get a reference to
> >> >> the flattened device tree.
> >> >>
> >> >> I'm not super familiar with device tree, but I was attempting to use
> >> >> fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a
> >> >> similar way that Quark does in my patchset (I've properly created the
> >> >> COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts
> >> >> file).  When I call fdtdec_next_compatible() the board does something
> >> >> which I'm unable to debug (Valley Island does not have the early UART
> >> >> pins connected so I have no early UART capability) but things just seem
> >> >> to stop.
> >> >>
> >> >> In manually tracing the calls which lead to update_fsp_upd(), it seems
> >> >> that we haven't yet set up global data, so it makes sense that I can't
> >> >> reference it.  But the device tree should be available in NOR flash or
> >> >> in some other way which we can access in order to get the FSP UPD
> >> >> settings.
> >> >>
> >> >> Is there a simple way to access the device tree while it's still in NOR
> >> >> flash so I can avoid using gd?  Or can global data be setup prior to
> >> >> calling update_fsp_upd() (I believe we're still in CAR at this point)?
> >> >> Or am I misunderstanding something basic here?
> >> >>
> >> >> Did you have a rough outline of how this could be moved to device tree?
> >> >
> >> > This is a bit tricky. I would like to move fsp_init() later in the
> >> > init sequence (e.g. to board_init_f()). See this TODO in the code:
> >> >
> >> > /*
> >> > * TODO:
> >> > *
> >> > * According to FSP architecture spec, the fsp_init() will not return
> >> > * to its caller, instead it requires the bootloader to provide a
> >> > * so-called continuation function to pass into the FSP as a parameter
> >> > * of fsp_init, and fsp_init() will call that continuation function
> >> > * directly.
> >> > *
> >> > * The call to fsp_init() may need to be moved out of the car_init()
> >> > * to cpu_init_f() with the help of some inline assembly codes.
> >> > * Note there is another issue that fsp_init() will setup another stack
> >> > * using the fsp_init parameter stack_top after DRAM is initialized,
> >> > * which means any data on the previous stack (on the CAR) gets lost
> >> > * (ie: U-Boot global_data). FSP is supposed to support such scenario,
> >> > * however it does not work. This should be revisited in the future.
> >> > */
> >> >
> >> > The primary issues are:
> >> > 1. The need to recover the global_data
> >> > 2. The need to change to a new stack
> >> >
> >> > Re 1, my reading of the HOB stuff is that it is supposed to provide
> >> > you with a pointer to the CAR RAM (all ~128KB of it) so that you can
> >> > go back and find your old stack (and in our case, global_data).
> >> >
> >> > Bin mentioned that this doesn't work - his is the comment above after
> >> > I asked him about it.
> >> >
> >> > But if it could be made to work, then we could delay the init.
> >> >
> >> > Re 2, U-Boot expects to change to a new stack when it wants to, which
> >> > is at the boundary of board_init_f() and board_init_r(). The Intel FSP
> >> > should not mandate a stack change over a C function call. IMO that is
> >> > just bad design. Dealing with it is not very easy, but one option is
> >> > to run with the new stack for the rest of the board_init_f() sequence
> >> > and then change stack again at the end of the sequence. Ick.
> >> >
> >> > To specifically address your problem, global_data is not available
> >> > until board_init_f() is called, and the device tree comes into
> >> > existence soon after. We could hack around it - e.g. with microcode we
> >> > find it in the device tree and stick a pointer to it in a special
> >> > place. But the real solution is to figure out how to move this
> >> > fsp_init() stuff to later in the sequence. For non-FSP boards we don't
> >> > have this problem - e.g. ivybridge does RAM init long after we have
> >> > global_data and device tree. Note it is still running from flash at
> >> > this point, but CAR is set up and that is where global_data resides.
> >> >
> >> > I'm interested to hear what you figure out.
> >> >
> >>
> >> I just noticed that Intel has released FSP specification v1.1 [1] in
> >> April. After a rough read of the 1.1 spec, it looks to me that Intel
> >> changed the fsp_init() design by breaking it down into 3 sub-routines:
> >> FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might
> >> be more logical to adapt U-Boot, but again I am not sure if the stack
> >> migration stuff is still there. So far I don't see any new FSP
> >> releases using the 1.1 spec.
> >>
> >> [1] https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-architecture-spec-v1-1.html
> >
> > There's also a very good overview of how to use an FSP v1.1 firmware at
> > [1].  It states that the problem in v1.0 for bootloaders was that when
> > you call FspInit() that temporary ram was torn down unconditionally.
> > Now, in v1.1, it says after calling FspMemoryInit() that control will be
> > given back to the bootloader running in the temporary ram (CAR?).  Then
> > the bootloader is responsible for migrating to main memory and to call
> > TempRamExit() so that temporary memory can be cleaned up.
> >
> > This sounds like what u-boot would want and what Simon described above,
> > for u-boot to be in charge of relocating from CAR to main memory, right?
> > If so, likely things will be much easier once there's a v1.1 FSP for
> > baytrail...
> >
> 
> Indeed, care to ping them to find out when this might happen?

I'm not sure, but I think Intel may have the source on Github [1].  I'm
starting to look through the code to see if it's actually useful for
E3800 parts or not, but a quick scan through the git log does show
changes to support FSP v1.1 and it appears to be actively developed...

[1]:https://github.com/tianocore/edk2-IntelFspPkg

Having a few other, more experienced, eyes on this to see if it's useful
would probably be good.

I will see what else I can find out about an FSP v1.1 release for E3800
parts, in the mean time.

Thanks!
-Andrew
Bin Meng May 29, 2015, 1:54 p.m. UTC | #12 
Hi Andrew, Simon,

On Fri, May 29, 2015 at 2:09 AM, Andrew Bradford
<andrew@bradfordembedded.com> wrote:
> On 05/28 10:30, Simon Glass wrote:
>> Hi Andrew,
>>
>> On 27 May 2015 at 08:39, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>> > On 05/27 13:19, Bin Meng wrote:
>> >> Hi Simon,
>> >>
>> >> On Wed, May 27, 2015 at 5:37 AM, Simon Glass <sjg@chromium.org> wrote:
>> >> > Hi Andrew,
>> >> >
>> >> > On 26 May 2015 at 13:52, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>> >> >> Hi Simon and Bin (sorry for bringing this back from the dead),
>> >> >>
>> >> >> But I have a question about fsp_configs.c down below:
>> >> >>
>> >> >> On 01/27 22:13, Simon Glass wrote:
>> >> >> ------------->8---------------

[snip]

>> >> >>
>> >> >> I am trying to move this fsp upd to use device tree as I am trying to
>> >> >> create a patch set to add the Intel Valley Island E38xx board (which
>> >> >> uses a SODIMM rather than memory down).  In doing so, I've found that
>> >> >> global data doesn't seem to be available when update_fsp_upd() is called
>> >> >> and generally it seems that gd->fdt_blob is used to get a reference to
>> >> >> the flattened device tree.
>> >> >>
>> >> >> I'm not super familiar with device tree, but I was attempting to use
>> >> >> fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a
>> >> >> similar way that Quark does in my patchset (I've properly created the
>> >> >> COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts
>> >> >> file).  When I call fdtdec_next_compatible() the board does something
>> >> >> which I'm unable to debug (Valley Island does not have the early UART
>> >> >> pins connected so I have no early UART capability) but things just seem
>> >> >> to stop.
>> >> >>
>> >> >> In manually tracing the calls which lead to update_fsp_upd(), it seems
>> >> >> that we haven't yet set up global data, so it makes sense that I can't
>> >> >> reference it.  But the device tree should be available in NOR flash or
>> >> >> in some other way which we can access in order to get the FSP UPD
>> >> >> settings.
>> >> >>
>> >> >> Is there a simple way to access the device tree while it's still in NOR
>> >> >> flash so I can avoid using gd?  Or can global data be setup prior to
>> >> >> calling update_fsp_upd() (I believe we're still in CAR at this point)?
>> >> >> Or am I misunderstanding something basic here?
>> >> >>
>> >> >> Did you have a rough outline of how this could be moved to device tree?
>> >> >
>> >> > This is a bit tricky. I would like to move fsp_init() later in the
>> >> > init sequence (e.g. to board_init_f()). See this TODO in the code:
>> >> >
>> >> > /*
>> >> > * TODO:
>> >> > *
>> >> > * According to FSP architecture spec, the fsp_init() will not return
>> >> > * to its caller, instead it requires the bootloader to provide a
>> >> > * so-called continuation function to pass into the FSP as a parameter
>> >> > * of fsp_init, and fsp_init() will call that continuation function
>> >> > * directly.
>> >> > *
>> >> > * The call to fsp_init() may need to be moved out of the car_init()
>> >> > * to cpu_init_f() with the help of some inline assembly codes.
>> >> > * Note there is another issue that fsp_init() will setup another stack
>> >> > * using the fsp_init parameter stack_top after DRAM is initialized,
>> >> > * which means any data on the previous stack (on the CAR) gets lost
>> >> > * (ie: U-Boot global_data). FSP is supposed to support such scenario,
>> >> > * however it does not work. This should be revisited in the future.
>> >> > */
>> >> >
>> >> > The primary issues are:
>> >> > 1. The need to recover the global_data
>> >> > 2. The need to change to a new stack
>> >> >
>> >> > Re 1, my reading of the HOB stuff is that it is supposed to provide
>> >> > you with a pointer to the CAR RAM (all ~128KB of it) so that you can
>> >> > go back and find your old stack (and in our case, global_data).
>> >> >
>> >> > Bin mentioned that this doesn't work - his is the comment above after
>> >> > I asked him about it.
>> >> >
>> >> > But if it could be made to work, then we could delay the init.
>> >> >
>> >> > Re 2, U-Boot expects to change to a new stack when it wants to, which
>> >> > is at the boundary of board_init_f() and board_init_r(). The Intel FSP
>> >> > should not mandate a stack change over a C function call. IMO that is
>> >> > just bad design. Dealing with it is not very easy, but one option is
>> >> > to run with the new stack for the rest of the board_init_f() sequence
>> >> > and then change stack again at the end of the sequence. Ick.
>> >> >
>> >> > To specifically address your problem, global_data is not available
>> >> > until board_init_f() is called, and the device tree comes into
>> >> > existence soon after. We could hack around it - e.g. with microcode we
>> >> > find it in the device tree and stick a pointer to it in a special
>> >> > place. But the real solution is to figure out how to move this
>> >> > fsp_init() stuff to later in the sequence. For non-FSP boards we don't
>> >> > have this problem - e.g. ivybridge does RAM init long after we have
>> >> > global_data and device tree. Note it is still running from flash at
>> >> > this point, but CAR is set up and that is where global_data resides.
>> >> >
>> >> > I'm interested to hear what you figure out.
>> >> >
>> >>
>> >> I just noticed that Intel has released FSP specification v1.1 [1] in
>> >> April. After a rough read of the 1.1 spec, it looks to me that Intel
>> >> changed the fsp_init() design by breaking it down into 3 sub-routines:
>> >> FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might
>> >> be more logical to adapt U-Boot, but again I am not sure if the stack
>> >> migration stuff is still there. So far I don't see any new FSP
>> >> releases using the 1.1 spec.
>> >>
>> >> [1] https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-architecture-spec-v1-1.html
>> >
>> > There's also a very good overview of how to use an FSP v1.1 firmware at
>> > [1].  It states that the problem in v1.0 for bootloaders was that when
>> > you call FspInit() that temporary ram was torn down unconditionally.
>> > Now, in v1.1, it says after calling FspMemoryInit() that control will be
>> > given back to the bootloader running in the temporary ram (CAR?).  Then
>> > the bootloader is responsible for migrating to main memory and to call
>> > TempRamExit() so that temporary memory can be cleaned up.
>> >
>> > This sounds like what u-boot would want and what Simon described above,
>> > for u-boot to be in charge of relocating from CAR to main memory, right?
>> > If so, likely things will be much easier once there's a v1.1 FSP for
>> > baytrail...
>> >
>>
>> Indeed, care to ping them to find out when this might happen?
>
> I'm not sure, but I think Intel may have the source on Github [1].  I'm
> starting to look through the code to see if it's actually useful for
> E3800 parts or not, but a quick scan through the git log does show
> changes to support FSP v1.1 and it appears to be actively developed...
>
> [1]:https://github.com/tianocore/edk2-IntelFspPkg
>

Looks like this is not the FSP source codes, but just the support
codes to get FSP integrated into the EDKII TianCore. I doubt Intel
will release any source codes of FSP.

> Having a few other, more experienced, eyes on this to see if it's useful
> would probably be good.
>

I will see if I can restart this FSP initialization sequence work next week.

> I will see what else I can find out about an FSP v1.1 release for E3800
> parts, in the mean time.
>

Regards,
Bin
Bin Meng June 1, 2015, 12:41 p.m. UTC | #13 
Hi Simon, Hi Andrew,

On Fri, May 29, 2015 at 9:54 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Andrew, Simon,
>
> On Fri, May 29, 2015 at 2:09 AM, Andrew Bradford
> <andrew@bradfordembedded.com> wrote:
>> On 05/28 10:30, Simon Glass wrote:
>>> Hi Andrew,
>>>
>>> On 27 May 2015 at 08:39, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>>> > On 05/27 13:19, Bin Meng wrote:
>>> >> Hi Simon,
>>> >>
>>> >> On Wed, May 27, 2015 at 5:37 AM, Simon Glass <sjg@chromium.org> wrote:
>>> >> > Hi Andrew,
>>> >> >
>>> >> > On 26 May 2015 at 13:52, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>>> >> >> Hi Simon and Bin (sorry for bringing this back from the dead),
>>> >> >>
>>> >> >> But I have a question about fsp_configs.c down below:
>>> >> >>
>>> >> >> On 01/27 22:13, Simon Glass wrote:
>>> >> >> ------------->8---------------
>
> [snip]
>
>>> >> >>
>>> >> >> I am trying to move this fsp upd to use device tree as I am trying to
>>> >> >> create a patch set to add the Intel Valley Island E38xx board (which
>>> >> >> uses a SODIMM rather than memory down).  In doing so, I've found that
>>> >> >> global data doesn't seem to be available when update_fsp_upd() is called
>>> >> >> and generally it seems that gd->fdt_blob is used to get a reference to
>>> >> >> the flattened device tree.
>>> >> >>
>>> >> >> I'm not super familiar with device tree, but I was attempting to use
>>> >> >> fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a
>>> >> >> similar way that Quark does in my patchset (I've properly created the
>>> >> >> COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts
>>> >> >> file).  When I call fdtdec_next_compatible() the board does something
>>> >> >> which I'm unable to debug (Valley Island does not have the early UART
>>> >> >> pins connected so I have no early UART capability) but things just seem
>>> >> >> to stop.
>>> >> >>
>>> >> >> In manually tracing the calls which lead to update_fsp_upd(), it seems
>>> >> >> that we haven't yet set up global data, so it makes sense that I can't
>>> >> >> reference it.  But the device tree should be available in NOR flash or
>>> >> >> in some other way which we can access in order to get the FSP UPD
>>> >> >> settings.
>>> >> >>
>>> >> >> Is there a simple way to access the device tree while it's still in NOR
>>> >> >> flash so I can avoid using gd?  Or can global data be setup prior to
>>> >> >> calling update_fsp_upd() (I believe we're still in CAR at this point)?
>>> >> >> Or am I misunderstanding something basic here?
>>> >> >>
>>> >> >> Did you have a rough outline of how this could be moved to device tree?
>>> >> >
>>> >> > This is a bit tricky. I would like to move fsp_init() later in the
>>> >> > init sequence (e.g. to board_init_f()). See this TODO in the code:
>>> >> >
>>> >> > /*
>>> >> > * TODO:
>>> >> > *
>>> >> > * According to FSP architecture spec, the fsp_init() will not return
>>> >> > * to its caller, instead it requires the bootloader to provide a
>>> >> > * so-called continuation function to pass into the FSP as a parameter
>>> >> > * of fsp_init, and fsp_init() will call that continuation function
>>> >> > * directly.
>>> >> > *
>>> >> > * The call to fsp_init() may need to be moved out of the car_init()
>>> >> > * to cpu_init_f() with the help of some inline assembly codes.
>>> >> > * Note there is another issue that fsp_init() will setup another stack
>>> >> > * using the fsp_init parameter stack_top after DRAM is initialized,
>>> >> > * which means any data on the previous stack (on the CAR) gets lost
>>> >> > * (ie: U-Boot global_data). FSP is supposed to support such scenario,
>>> >> > * however it does not work. This should be revisited in the future.
>>> >> > */
>>> >> >
>>> >> > The primary issues are:
>>> >> > 1. The need to recover the global_data
>>> >> > 2. The need to change to a new stack
>>> >> >
>>> >> > Re 1, my reading of the HOB stuff is that it is supposed to provide
>>> >> > you with a pointer to the CAR RAM (all ~128KB of it) so that you can
>>> >> > go back and find your old stack (and in our case, global_data).
>>> >> >
>>> >> > Bin mentioned that this doesn't work - his is the comment above after
>>> >> > I asked him about it.
>>> >> >
>>> >> > But if it could be made to work, then we could delay the init.
>>> >> >
>>> >> > Re 2, U-Boot expects to change to a new stack when it wants to, which
>>> >> > is at the boundary of board_init_f() and board_init_r(). The Intel FSP
>>> >> > should not mandate a stack change over a C function call. IMO that is
>>> >> > just bad design. Dealing with it is not very easy, but one option is
>>> >> > to run with the new stack for the rest of the board_init_f() sequence
>>> >> > and then change stack again at the end of the sequence. Ick.
>>> >> >
>>> >> > To specifically address your problem, global_data is not available
>>> >> > until board_init_f() is called, and the device tree comes into
>>> >> > existence soon after. We could hack around it - e.g. with microcode we
>>> >> > find it in the device tree and stick a pointer to it in a special
>>> >> > place. But the real solution is to figure out how to move this
>>> >> > fsp_init() stuff to later in the sequence. For non-FSP boards we don't
>>> >> > have this problem - e.g. ivybridge does RAM init long after we have
>>> >> > global_data and device tree. Note it is still running from flash at
>>> >> > this point, but CAR is set up and that is where global_data resides.
>>> >> >
>>> >> > I'm interested to hear what you figure out.
>>> >> >
>>> >>
>>> >> I just noticed that Intel has released FSP specification v1.1 [1] in
>>> >> April. After a rough read of the 1.1 spec, it looks to me that Intel
>>> >> changed the fsp_init() design by breaking it down into 3 sub-routines:
>>> >> FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might
>>> >> be more logical to adapt U-Boot, but again I am not sure if the stack
>>> >> migration stuff is still there. So far I don't see any new FSP
>>> >> releases using the 1.1 spec.
>>> >>
>>> >> [1] https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-architecture-spec-v1-1.html
>>> >
>>> > There's also a very good overview of how to use an FSP v1.1 firmware at
>>> > [1].  It states that the problem in v1.0 for bootloaders was that when
>>> > you call FspInit() that temporary ram was torn down unconditionally.
>>> > Now, in v1.1, it says after calling FspMemoryInit() that control will be
>>> > given back to the bootloader running in the temporary ram (CAR?).  Then
>>> > the bootloader is responsible for migrating to main memory and to call
>>> > TempRamExit() so that temporary memory can be cleaned up.
>>> >
>>> > This sounds like what u-boot would want and what Simon described above,
>>> > for u-boot to be in charge of relocating from CAR to main memory, right?
>>> > If so, likely things will be much easier once there's a v1.1 FSP for
>>> > baytrail...
>>> >
>>>
>>> Indeed, care to ping them to find out when this might happen?
>>
>> I'm not sure, but I think Intel may have the source on Github [1].  I'm
>> starting to look through the code to see if it's actually useful for
>> E3800 parts or not, but a quick scan through the git log does show
>> changes to support FSP v1.1 and it appears to be actively developed...
>>
>> [1]:https://github.com/tianocore/edk2-IntelFspPkg
>>
>
> Looks like this is not the FSP source codes, but just the support
> codes to get FSP integrated into the EDKII TianCore. I doubt Intel
> will release any source codes of FSP.
>
>> Having a few other, more experienced, eyes on this to see if it's useful
>> would probably be good.
>>
>
> I will see if I can restart this FSP initialization sequence work next week.
>

I've reworked the FSP initialization sequence so that now it is called
by board_init_f(). I tested it on Crown Bay. Would you please try the
following two patches and see if it works on the MinnowMax board?

http://patchwork.ozlabs.org/patch/478943/
http://patchwork.ozlabs.org/patch/478944/

[snip]

Regards,
Bin
Andrew Bradford June 11, 2015, 11:34 a.m. UTC | #14 
Hi Simon,

On 05/28 10:30, Simon Glass wrote:
> Hi Andrew,
> 
> On 27 May 2015 at 08:39, Andrew Bradford <andrew@bradfordembedded.com> wrote:
> > On 05/27 13:19, Bin Meng wrote:
> >> Hi Simon,

------------->8--------------

> >> I just noticed that Intel has released FSP specification v1.1 [1] in
> >> April. After a rough read of the 1.1 spec, it looks to me that Intel
> >> changed the fsp_init() design by breaking it down into 3 sub-routines:
> >> FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might
> >> be more logical to adapt U-Boot, but again I am not sure if the stack
> >> migration stuff is still there. So far I don't see any new FSP
> >> releases using the 1.1 spec.
> >>
> >> [1] https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-architecture-spec-v1-1.html
> >
> > There's also a very good overview of how to use an FSP v1.1 firmware at
> > [1].  It states that the problem in v1.0 for bootloaders was that when
> > you call FspInit() that temporary ram was torn down unconditionally.
> > Now, in v1.1, it says after calling FspMemoryInit() that control will be
> > given back to the bootloader running in the temporary ram (CAR?).  Then
> > the bootloader is responsible for migrating to main memory and to call
> > TempRamExit() so that temporary memory can be cleaned up.
> >
> > This sounds like what u-boot would want and what Simon described above,
> > for u-boot to be in charge of relocating from CAR to main memory, right?
> > If so, likely things will be much easier once there's a v1.1 FSP for
> > baytrail...
> >
> 
> Indeed, care to ping them to find out when this might happen?

It seems like there are no current plans to implement an FSP v1.1 compliant
firmware release for Bay Trail [1], which is unfortunate.

[1]:https://embedded.communities.intel.com/thread/8218

I will continue to pester my contacts at Intel.

Thanks,
Andrew
diff mbox

Patch

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 1b7955b..3e0d809 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -41,6 +41,17 @@  config TARGET_CROWNBAY
 	  Intel Platform Controller Hub EG20T, other system components and
 	  peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
 
+config TARGET_MINNOWMAX
+	bool "Support Intel Minnowboard MAX"
+	help
+	  This is the Intel Minnowboard MAX. It contains an Atom E3800
+	  processor in a small form factor with Ethernet, micro-SD, USB 2,
+	  USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
+	  It requires some binary blobs - see README.x86 for details.
+
+	  Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+	  by U-Boot matches that value.
+
 endchoice
 
 config RAMBASE
@@ -382,6 +393,8 @@  config FSP_TEMP_RAM_ADDR
 	  Stack top address which is used in FspInit after DRAM is ready and
 	  CAR is disabled.
 
+source "arch/x86/cpu/baytrail/Kconfig"
+
 source "arch/x86/cpu/coreboot/Kconfig"
 
 source "arch/x86/cpu/ivybridge/Kconfig"
@@ -394,6 +407,8 @@  source "board/google/chromebook_link/Kconfig"
 
 source "board/intel/crownbay/Kconfig"
 
+source "board/intel/minnowmax/Kconfig"
+
 config PCIE_ECAM_BASE
 	hex
         default 0xe0000000
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 62e43c0..5acf8bb 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -12,6 +12,7 @@  extra-y	= start.o
 obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
 obj-y	+= interrupts.o cpu.o call64.o
 
+obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
 obj-$(CONFIG_SYS_COREBOOT) += coreboot/
 obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
 obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig
new file mode 100644
index 0000000..e86cc01
--- /dev/null
+++ b/arch/x86/cpu/baytrail/Kconfig
@@ -0,0 +1,9 @@ 
+#
+# Copyright (C) 2015 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+config INTEL_BAYTRAIL
+	bool
+	select HAVE_FSP
diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
new file mode 100644
index 0000000..8914e8b
--- /dev/null
+++ b/arch/x86/cpu/baytrail/Makefile
@@ -0,0 +1,10 @@ 
+#
+# Copyright (C) 2015 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += early_uart.o
+obj-y += fsp_configs.o
+obj-y += pci.o
+obj-y += valleyview.o
diff --git a/arch/x86/cpu/baytrail/early_uart.c b/arch/x86/cpu/baytrail/early_uart.c
new file mode 100644
index 0000000..0144323
--- /dev/null
+++ b/arch/x86/cpu/baytrail/early_uart.c
@@ -0,0 +1,78 @@ 
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <errno.h>
+#include <asm/io.h>
+
+#define PCI_DEV_CONFIG(segbus, dev, fn) ( \
+		(((segbus) & 0xfff) << 20) | \
+		(((dev) & 0x1f) << 15) | \
+		(((fn)  & 0x07) << 12))
+
+/* Platform Controller Unit */
+#define LPC_DEV			0x1f
+#define LPC_FUNC		0
+
+/* Enable UART */
+#define UART_CONT		0x80
+
+/* SCORE Pad definitions */
+#define UART_RXD_PAD			82
+#define UART_TXD_PAD			83
+
+/* Pad base: PAD_CONF0[n]= PAD_BASE + 16 * n */
+#define GPSCORE_PAD_BASE	(IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE)
+
+/* IO Memory */
+#define IO_BASE_ADDRESS			0xfed0c000
+#define  IO_BASE_OFFSET_GPSCORE		0x0000
+#define  IO_BASE_OFFSET_GPNCORE		0x1000
+#define  IO_BASE_OFFSET_GPSSUS		0x2000
+#define IO_BASE_SIZE			0x4000
+
+static inline unsigned int score_pconf0(int pad_num)
+{
+	return GPSCORE_PAD_BASE + pad_num * 16;
+}
+
+static void score_select_func(int pad, int func)
+{
+	uint32_t reg;
+	uint32_t pconf0_addr = score_pconf0(pad);
+
+	reg = readl(pconf0_addr);
+	reg &= ~0x7;
+	reg |= func & 0x7;
+	writel(reg, pconf0_addr);
+}
+
+static void pci_write_config32(int dev, unsigned int where, u32 value)
+{
+	unsigned long addr;
+
+	addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
+	writel(value, addr);
+}
+
+/* This can be called after memory-mapped PCI is working */
+int setup_early_uart(void)
+{
+	/* Enable the legacy UART hardware. */
+	pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, 1);
+
+	/*
+	 * Set up the pads to the UART function. This allows the signals to
+	 * leave the chip
+	 */
+	score_select_func(UART_RXD_PAD, 1);
+	score_select_func(UART_TXD_PAD, 1);
+
+	debug_uart_init();
+
+	return 0;
+}
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
new file mode 100644
index 0000000..86b6926
--- /dev/null
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -0,0 +1,156 @@ 
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	Intel
+ */
+
+#include <common.h>
+#include <asm/arch/fsp/azalia.h>
+#include <asm/fsp/fsp_support.h>
+
+/* ALC262 Verb Table - 10EC0262 */
+static const uint32_t verb_table_data13[] = {
+	/* Pin Complex (NID 0x11) */
+	0x01171cf0,
+	0x01171d11,
+	0x01171e11,
+	0x01171f41,
+	/* Pin Complex (NID 0x12) */
+	0x01271cf0,
+	0x01271d11,
+	0x01271e11,
+	0x01271f41,
+	/* Pin Complex (NID 0x14) */
+	0x01471c10,
+	0x01471d40,
+	0x01471e01,
+	0x01471f01,
+	/* Pin Complex (NID 0x15) */
+	0x01571cf0,
+	0x01571d11,
+	0x01571e11,
+	0x01571f41,
+	/* Pin Complex (NID 0x16) */
+	0x01671cf0,
+	0x01671d11,
+	0x01671e11,
+	0x01671f41,
+	/* Pin Complex (NID 0x18) */
+	0x01871c20,
+	0x01871d98,
+	0x01871ea1,
+	0x01871f01,
+	/* Pin Complex (NID 0x19) */
+	0x01971c21,
+	0x01971d98,
+	0x01971ea1,
+	0x01971f02,
+	/* Pin Complex (NID 0x1A) */
+	0x01a71c2f,
+	0x01a71d30,
+	0x01a71e81,
+	0x01a71f01,
+	/* Pin Complex */
+	0x01b71c1f,
+	0x01b71d40,
+	0x01b71e21,
+	0x01b71f02,
+	/* Pin Complex */
+	0x01c71cf0,
+	0x01c71d11,
+	0x01c71e11,
+	0x01c71f41,
+	/* Pin Complex */
+	0x01d71c01,
+	0x01d71dc6,
+	0x01d71e14,
+	0x01d71f40,
+	/* Pin Complex */
+	0x01e71cf0,
+	0x01e71d11,
+	0x01e71e11,
+	0x01e71f41,
+	/* Pin Complex */
+	0x01f71cf0,
+	0x01f71d11,
+	0x01f71e11,
+	0x01f71f41,
+};
+
+/*
+ * This needs to be in ROM since if we put it in CAR, FSP init loses it when
+ * it drops CAR.
+ *
+ * TODO(sjg@chromium.org): Move to device tree when FSP allows it
+ *
+ * VerbTable: (RealTek ALC262)
+ * Revision ID = 0xFF, support all steps
+ * Codec Verb Table For AZALIA
+ * Codec Address: CAd value (0/1/2)
+ * Codec Vendor: 0x10EC0262
+ */
+static const struct pch_azalia_verb_table azalia_verb_table[] = {
+	{
+		{
+			0x10ec0262,
+			0x0000,
+			0xff,
+			0x01,
+			0x000b,
+			0x0002,
+		},
+		verb_table_data13
+	}
+};
+
+const struct pch_azalia_config azalia_config = {
+	.pme_enable = 1,
+	.docking_supported = 1,
+	.docking_attached = 0,
+	.hdmi_codec_enable = 1,
+	.azalia_v_ci_enable = 1,
+	.rsvdbits = 0,
+	.azalia_verb_table_num = 1,
+	.azalia_verb_table = azalia_verb_table,
+	.reset_wait_timer_us = 300
+};
+
+void update_fsp_upd(struct upd_region *fsp_upd)
+{
+	struct memory_down_data *mem;
+
+	/*
+	 * Configure everything here to avoid the poor hard-pressed user
+	 * needing to run Intel's binary configuration tool. It may also allow
+	 * us to support the 1GB single core variant easily.
+	 *
+	 * TODO(sjg@chromium.org): Move to device tree
+	 */
+	fsp_upd->mrc_init_tseg_size = 8;
+	fsp_upd->mrc_init_mmio_size = 0x800;
+	fsp_upd->emmc_boot_mode = 0xff;
+	fsp_upd->enable_sdio = 1;
+	fsp_upd->enable_sdcard = 1;
+	fsp_upd->enable_hsuart0 = 1;
+	fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
+	fsp_upd->enable_i2_c0 = 0;
+	fsp_upd->enable_i2_c2 = 0;
+	fsp_upd->enable_i2_c3 = 0;
+	fsp_upd->enable_i2_c4 = 0;
+	fsp_upd->enable_xhci = 0;
+	fsp_upd->igd_render_standby = 1;
+
+	mem = &fsp_upd->memory_params;
+	mem->enable_memory_down = 1;
+	mem->dram_speed = 1;
+	mem->dimm_width = 1;
+	mem->dimm_density = 2;
+	mem->dimm_tcl = 0xb;
+	mem->dimm_trpt_rcd = 0xb;
+	mem->dimm_twr = 0xc;
+	mem->dimm_twtr = 6;
+	mem->dimm_trrd = 6;
+	mem->dimm_trtp = 6;
+	mem->dimm_tfaw = 0x14;
+}
diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c
new file mode 100644
index 0000000..7032c97
--- /dev/null
+++ b/arch/x86/cpu/baytrail/pci.c
@@ -0,0 +1,47 @@ 
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_pci_setup_hose(struct pci_controller *hose)
+{
+	hose->first_busno = 0;
+	hose->last_busno = 0;
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 0,
+		       CONFIG_PCI_MEM_BUS,
+		       CONFIG_PCI_MEM_PHYS,
+		       CONFIG_PCI_MEM_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 1,
+		       CONFIG_PCI_IO_BUS,
+		       CONFIG_PCI_IO_PHYS,
+		       CONFIG_PCI_IO_SIZE,
+		       PCI_REGION_IO);
+
+	pci_set_region(hose->regions + 2,
+		       CONFIG_PCI_PREF_BUS,
+		       CONFIG_PCI_PREF_PHYS,
+		       CONFIG_PCI_PREF_SIZE,
+		       PCI_REGION_PREFETCH);
+
+	pci_set_region(hose->regions + 3,
+		       0,
+		       0,
+		       gd->ram_size,
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	hose->region_count = 4;
+}
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
new file mode 100644
index 0000000..a3e837d
--- /dev/null
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -0,0 +1,38 @@ 
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <pci_ids.h>
+#include <asm/post.h>
+
+static struct pci_device_id mmc_supported[] = {
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
+};
+
+int cpu_mmc_init(bd_t *bis)
+{
+	printf("mmc init\n");
+	return pci_mmc_init("ValleyView SDHCI", mmc_supported,
+			    ARRAY_SIZE(mmc_supported));
+}
+
+int arch_cpu_init(void)
+{
+	int ret;
+
+	post_code(POST_CPU_INIT);
+#ifdef CONFIG_SYS_X86_TSC_TIMER
+	timer_set_base(rdtsc());
+#endif
+
+	ret = x86_cpu_init_f();
+	if (ret)
+		return ret;
+
+	return 0;
+}
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 97ed884..4e0171a 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -1,5 +1,6 @@ 
 dtb-y += chromebook_link.dtb \
-	crownbay.dtb
+	crownbay.dtb \
+	minnowmax.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/x86/dts/microcode/m0130673322.dtsi b/arch/x86/dts/microcode/m0130673322.dtsi
new file mode 100644
index 0000000..90bf2fb
--- /dev/null
+++ b/arch/x86/dts/microcode/m0130673322.dtsi
@@ -0,0 +1,3284 @@ 
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x322>;
+intel,date-code = <0x4012014>;
+intel,processor-signature = <0x30673>;
+intel,checksum = <0x17b0d914>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x22030000	0x14200104	0x73060300
+	0x14d9b017	0x01000000	0x01000000	0xd0cb0000
+	0x00cc0000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x22030000
+	0x00000000	0x00000000	0x31031420	0x11320000
+	0x01000000	0x73060300	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xf4320000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x0ae10178	0x7c98f9d1	0x41962d85	0x19391270
+	0xcf3c0336	0xc1f13d6f	0xe46abaf6	0x3b65ca6b
+	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
+	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
+	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
+	0xc928c400	0x3add156d	0x531946f9	0x92a03216
+	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
+	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
+	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
+	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
+	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
+	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
+	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
+	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
+	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
+	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
+	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
+	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
+	0x11000000	0x8514b971	0x40df7b4a	0x6a6b7285
+	0x7978ef59	0x319bddf5	0x04c68e5a	0xe1c28b10
+	0x172f63dc	0x306fb95d	0x31d881e8	0x69f8e08d
+	0x617a99e1	0x1ab6b574	0x2951fa5b	0xcc7e3e94
+	0xff379d19	0x5c035dec	0xe28ed726	0x22b8a5ac
+	0xd08b3ac5	0x45c03b9e	0xcea4083c	0xc26758aa
+	0xbe7cf81e	0x43d898f3	0x5c45a635	0xc9cac095
+	0xb89aea20	0x2c02b40e	0xe3a8b48d	0xeabfb60e
+	0x776ed2a9	0x080ae6d5	0x7f64b1df	0x00e40ee6
+	0x0f1c10f4	0x792e5423	0x787f5459	0x63a8b02c
+	0x3fd6a255	0x049cae26	0x0949f5ff	0x9aebb236
+	0xecc01775	0x91b57b84	0xe0e45ea3	0x5a8bf79e
+	0x356a843a	0x2406795f	0x8aaae5d8	0x6a8c877c
+	0xa8b2b8f4	0x04cf8f49	0x422d9e2c	0xf09f9896
+	0xe9b92215	0x9c98fb44	0x88556b7f	0x519d6f4c
+	0x9e8a016b	0xcb18d16c	0x419b4ee7	0x080b49c8
+	0xc51b875e	0x46aabc9c	0x262d27eb	0x93ea189d
+	0xdd0da69d	0x3e5b17e8	0xcc78509a	0x00b07e6e
+	0x363d5a70	0x64572070	0x8a84abc4	0x1cb03838
+	0x965fd76a	0x540aafc9	0x83a91654	0x1a722e67
+	0x4bf98ce1	0x2b3c2ff9	0x972cebd4	0xf3a68395
+	0x2613e422	0xf8d031d7	0xb1c79a0f	0xfd44f65b
+	0xa7012a9b	0xd9a15a60	0xc311fc0c	0x6f52f878
+	0x3d68381d	0xd2a035d7	0xb790c50e	0x9f1e5010
+	0x41877064	0xa9d1e4ae	0xfe9abbd5	0x60c2c748
+	0x8167e5ad	0x022dbfb3	0x75abe483	0x51c37170
+	0x09b8590d	0xc1bb323d	0x2c7336b1	0xd4d0d49b
+	0xc7f6152b	0x7919d596	0x1e1ff62e	0xc49604a0
+	0x33857369	0xeaa3f382	0x98b8cd86	0x176e1bf3
+	0x1a68867b	0x6af0a11c	0x69a82b25	0x48c72525
+	0xa00aae2d	0xb09f67f4	0x1a99f83d	0x7266cca3
+	0x8d03a7da	0x2e1d7c49	0x01ac68ae	0x93188770
+	0x0609e769	0x982ed28d	0xe40999e0	0x8932ebab
+	0x5637ad5a	0x2725e8ad	0x56d7caaf	0xc351faa2
+	0x09dbd737	0x0d2f3bf0	0x0623330d	0xdd547489
+	0xcca7e722	0xa9096d13	0x95b17818	0xc092cb81
+	0x72c6eefc	0x1811c37e	0x78161497	0x8be0c4c6
+	0xd63aeb19	0x91ab68df	0x8f2e5e4d	0xf4c74566
+	0x7677a553	0x19698ac3	0xedca0620	0x77f32470
+	0x031e011b	0x751f6696	0xb277d06e	0x3eae2742
+	0x133e621a	0x38fa3172	0x9398cc1c	0xf42a507b
+	0x4547d933	0x63a91eb0	0xf5bcf6a4	0x926ba056
+	0x0adf5bce	0x140f53e4	0x7ff6bb5c	0x87dd79ba
+	0xbba240ac	0x694f743d	0x709cdb20	0x5b4d4401
+	0xc9693610	0x55f9f268	0x1142bc3f	0xf8fe3689
+	0x04a93c4c	0x33dedc46	0xdc73c725	0x2f5ba264
+	0x5b7a6a69	0x024b64f5	0x6e8bfa12	0x62bf2aa7
+	0x520f5a07	0x3c7c4292	0xb7ad2613	0x1f78fc87
+	0xd5284e4e	0x2c730f33	0x8861e947	0x8bacef7d
+	0xbafa2608	0x14ed0b5b	0x3b9bfb02	0x24ced271
+	0x002b2941	0x22d4431c	0x855f4248	0x5ec46e29
+	0x6f1f42fb	0x5dd24fe0	0x290961f6	0xf392dbaf
+	0xa1a8d9c2	0x61e18f4e	0xfda59a70	0x5498daa5
+	0x5ae7ea6f	0xf058c635	0x6817ebee	0x8e30dc8b
+	0x7c8d79be	0x5fb15b9b	0xeed64741	0xe2642a94
+	0x680d7e6e	0x3cbad7aa	0x808c415f	0xe9323aa2
+	0xaadf5b25	0xf60abf13	0xd5c47967	0xc248d0b3
+	0x0f232cbd	0x84092449	0x5744384b	0x5e153ded
+	0x8bb19817	0x34430271	0x917d2315	0x1fc790c7
+	0xc21b5db6	0xec578b1f	0x903a286e	0xca0c59bc
+	0x03e95c7a	0x8c659e99	0x7b09da0a	0xd61e7517
+	0x90b1c519	0x8deac92c	0xf99c7bec	0xb6257d92
+	0x3d61c16e	0xebd58be0	0xb470e655	0xa44bbf4f
+	0xfebe5313	0x4662110a	0x5d42ccd9	0x140845ec
+	0xc80329a9	0x915ca966	0x71e33828	0xe46c870a
+	0x7da9a490	0x255544da	0xa20fb8df	0xf94062b3
+	0xb2df5870	0xebf31e88	0x6e723e2f	0xe6ba9cf1
+	0x7e7084c2	0x1782ac71	0x0a0b0127	0xe9234e38
+	0x881356d6	0xb27a54b6	0x5594730e	0x9a14bd8f
+	0x6dba7da9	0x1069e285	0x02a52798	0x61ea7d86
+	0x665b2572	0x29d41eb5	0x1d211169	0x1218b345
+	0xbfbd264c	0x5b8b0625	0xbbfdcf39	0x6768dfce
+	0x0b5f10cb	0xe159414c	0x74356ed6	0x70077f49
+	0x672107e8	0x11616856	0x824e6f2f	0x99614958
+	0x5857305d	0x416a193f	0x010d266c	0xe5194f03
+	0x152d6516	0xeb83872e	0x4923cc1f	0x1191d1ca
+	0x23feb738	0x6817c1d7	0xe49129ed	0x4a53132a
+	0xdb46b95b	0x3f970366	0x93f1a518	0xae8d72ae
+	0xb689d915	0x0bdfda17	0x2ac7238d	0x1c4291e7
+	0xc5b11085	0x3c51c1ba	0x9fd63edd	0xe464d740
+	0xc17f2789	0x0adef6b9	0xf9aaf83e	0xfb2a9798
+	0x7f16268b	0x4c8ca6c5	0x2b17be52	0x00c91157
+	0xb69eb5db	0xe55ed94a	0xdf13b5a5	0xbb52d1e3
+	0x651bb017	0xc7795724	0x0dfd4711	0x02d2d6e0
+	0xc835e771	0x8ab5dd50	0x7caca109	0xd5c18d6e
+	0xbef0e727	0xaff2dd07	0xf1062a32	0x26d14796
+	0x97f6e36c	0xf845278e	0x185eb5b3	0xcde4e201
+	0x13166ab7	0xcdcebcdc	0x143ef0c7	0x2349893f
+	0x9dfcb70e	0x7ef72725	0x141c5b71	0x7da0f5d3
+	0x76bebb67	0x28bc0a83	0xb67ecf0f	0xd60a1303
+	0x9391b279	0x6ad41154	0x317896b0	0x1237efa6
+	0x7b2a2e6c	0x3ad9a110	0xb44357d4	0xb32e39fe
+	0x2358d28e	0x76e847d9	0x3e85db01	0x6c74e466
+	0x9e4e6b32	0x13072a53	0x5972132e	0xd97cb04d
+	0x55ee6a0b	0xc1434b92	0x772f6a1d	0x0f81f7a6
+	0x072aa8f7	0x179da0e0	0x976bd78c	0x2e43c16b
+	0x4f4a6b51	0x92d9c61b	0xa9c15fe4	0x3f8a527a
+	0x3a232408	0x543d7957	0x21cbd682	0x896de3b0
+	0xba6b3df6	0x2ec86e51	0x2be889e3	0xae764ff0
+	0x3a2f0003	0x7a5f7949	0x577fb5ce	0xb5cbd1a6
+	0xc910ffe2	0x7fd76712	0xfc1e93ff	0xbee7b15c
+	0x5db2356d	0x9721a3fd	0x0d408aed	0x4df4c922
+	0x45d5be91	0x6c79b1fc	0xf0bf73bd	0x3f6a73b6
+	0xdcc1b51e	0x2049fe2d	0xf2b2ad4b	0xd0484d3a
+	0x1f097d3f	0xced1bf3d	0x10f4416b	0x73cb307c
+	0x4b4d94b4	0x2918ece0	0x0cfe69f3	0xb7e86cfb
+	0xa6c373b4	0x0d862b62	0x1735cd72	0xef23c127
+	0x09809c16	0x86cfb70b	0xe67c6903	0x743223a7
+	0x13c7d27f	0xb70a58cc	0x82c57566	0x2ead3c65
+	0xf9409863	0xf2b578ef	0x1622a34d	0x5ae8e861
+	0xf4384016	0x443ff5f4	0x088b8510	0xd738d1c5
+	0x577d624b	0x5adf3973	0x5f79add3	0xed7e7145
+	0x29008fc0	0xd5b278cf	0x5b4c08c2	0xb063af5c
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+	0x2d8f8767	0x2036685b	0x149df155	0x2e7ab376
+	0xb13b4266	0xf5c8a3b0	0x02ca1e19	0x1badd81b
+	0xb9c1832a	0x73b31f75	0x69979b55	0x567070a2
+	0x2edeb3dc	0x26b55921	0x461df49f	0xc1aba883
+	0x25d6faec	0x5260e9bf	0xa8ccdd4c	0x04291961
+	0xfaf7a1b8	0xbc2d36e3	0xd6c86385	0x2757fbb9
+	0x62c7107c	0x87dac461	0x0c006454	0x0e971e49
+	0x4749afca	0x7f1fb389	0xdc0b69d3	0xc69fab09
+	0x12c372c9	0x78480a51	0x8ab03a94	0xb37022ca
+	0x1d00e893	0x0989de45	0x8c819503	0x8e0e1c06
+	0x11cfef86	0x3c2386a6	0x66c0e6c8	0x1befa478
+	0xd2e7a4a7	0x9a8b5917	0x2cfa1816	0xaf7e6c7a
+	0xd6c9f0ff	0x1aada3e0	0xbe36a471	0x5a91f3c7
+	0x6c61ea95	0x5246ef7c	0x20bc86c4	0xcfd87abd
+	0xdc61f595	0x8310a684	0x0477e35c	0xe59e776f
+	0xfa403863	0xdaf7bcb1	0xd6084825	0xb90bb047
+	0xeb9ff684	0x7223fbca	0x6b4af987	0x6b2553f8
+	0xdaabc6d2	0x82e2ebc3	0xa7c1c054	0x667eb0a7
+	0x53a0c7d4	0x3fcba743	0x38170187	0x2a2e5830
+	0xee134608	0xcd6e0112	0xac0831f9	0x9537d532
+	0x1e176b9c	0xe3fcb69f	0x17a2eee9	0xa9e6467f
+	0xbf6b0246	0x6a08c0fb	0x7fb943b6	0xb8f67c0e
+	0x2b3b4ffc	0xb155d20c	0x4eb5de53	0xf078715b
+	>;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
new file mode 100644
index 0000000..8f34369
--- /dev/null
+++ b/arch/x86/dts/minnowmax.dts
@@ -0,0 +1,45 @@ 
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+
+/ {
+	model = "Intel Minnowboard Max";
+	compatible = "intel,minnowmax", "intel,baytrail";
+
+	aliases {
+		serial0 = &serial;
+	};
+
+	config {
+		silent_console = <0>;
+	};
+
+	chosen {
+		stdout-path = "/serial";
+	};
+
+	spi {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "intel,ich";
+		spi-flash@0 {
+			reg = <0>;
+			compatible = "sst,25vf016b", "spi-flash";
+			memory-map = <0xff800000 0x00800000>;
+		};
+	};
+
+	microcode {
+		update@0 {
+#include "microcode/m0130673322.dtsi"
+		};
+	};
+
+};
diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi
index 9b097f4..6865eed 100644
--- a/arch/x86/dts/serial.dtsi
+++ b/arch/x86/dts/serial.dtsi
@@ -1,5 +1,5 @@ 
 / {
-	serial {
+	serial: serial {
 		compatible = "x86-uart";
 		reg = <0x3f8 8>;
 		reg-shift = <0>;
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h
new file mode 100644
index 0000000..d96a20f
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h
@@ -0,0 +1,39 @@ 
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	Intel
+ */
+
+#ifndef _FSP_AZALIA_H_
+#define _FSP_AZALIA_H_
+
+struct __packed pch_azalia_verb_table_header {
+	uint32_t vendor_device_id;
+	uint16_t sub_system_id;
+	uint8_t revision_id;		/* 0xff applies to all steppings */
+	uint8_t front_panel_support;
+	uint16_t number_of_rear_jacks;
+	uint16_t number_of_front_jacks;
+};
+
+struct __packed pch_azalia_verb_table {
+	struct pch_azalia_verb_table_header verb_table_header;
+	const uint32_t *verb_table_data;
+};
+
+struct __packed pch_azalia_config {
+	uint8_t pme_enable:1;
+	uint8_t docking_supported:1;
+	uint8_t docking_attached:1;
+	uint8_t hdmi_codec_enable:1;
+	uint8_t azalia_v_ci_enable:1;
+	uint8_t rsvdbits:3;
+	/* number of verb tables provided by platform */
+	uint8_t azalia_verb_table_num;
+	const struct pch_azalia_verb_table *azalia_verb_table;
+	/* delay timer after azalia reset */
+	uint16_t reset_wait_timer_us;
+};
+
+#endif
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
new file mode 100644
index 0000000..82862f6
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
@@ -0,0 +1,95 @@ 
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	Intel
+ */
+
+#ifndef __FSP_VPD_H
+#define __FSP_VPD_H
+
+struct memory_down_data {
+	uint8_t enable_memory_down;
+	uint8_t dram_speed;
+	uint8_t dram_type;
+	uint8_t dimm_0_enable;
+	uint8_t dimm_1_enable;
+	uint8_t dimm_width;
+	uint8_t dimm_density;
+	uint8_t dimm_bus_width;
+	uint8_t dimm_sides;			/* Ranks Per dimm_ */
+	uint8_t dimm_tcl;			/* tCL */
+	/* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
+	uint8_t dimm_trpt_rcd;
+	uint8_t dimm_twr;			/* tWR in DRAM clk  */
+	uint8_t dimm_twtr;			/* tWTR in DRAM clk */
+	uint8_t dimm_trrd;			/* tRRD in DRAM clk */
+	uint8_t dimm_trtp;			/* tRTP in DRAM clk */
+	uint8_t dimm_tfaw;			/* tFAW in DRAM clk */
+};
+
+struct __packed upd_region {
+	uint64_t signature;			/* Offset 0x0000 */
+	uint8_t reserved0[24];			/* Offset 0x0008 */
+	uint16_t mrc_init_tseg_size;		/* Offset 0x0020 */
+	uint16_t mrc_init_mmio_size;		/* Offset 0x0022 */
+	uint8_t mrc_init_spd_addr1;		/* Offset 0x0024 */
+	uint8_t mrc_init_spd_addr2;		/* Offset 0x0025 */
+	uint8_t emmc_boot_mode;			/* Offset 0x0026 */
+	uint8_t enable_sdio;			/* Offset 0x0027 */
+	uint8_t enable_sdcard;			/* Offset 0x0028 */
+	uint8_t enable_hsuart0;			/* Offset 0x0029 */
+	uint8_t enable_hsuart1;			/* Offset 0x002a */
+	uint8_t enable_spi;			/* Offset 0x002b */
+	uint8_t reserved1;			/* Offset 0x002c */
+	uint8_t enable_sata;			/* Offset 0x002d */
+	uint8_t sata_mode;			/* Offset 0x002e */
+	uint8_t enable_azalia;			/* Offset 0x002f */
+	uint32_t azalia_config_ptr;		/* Offset 0x0030 */
+	uint8_t enable_xhci;			/* Offset 0x0034 */
+	uint8_t enable_lpe;			/* Offset 0x0035 */
+	uint8_t lpss_sio_enable_pci_mode;	/* Offset 0x0036 */
+	uint8_t enable_dma0;			/* Offset 0x0037 */
+	uint8_t enable_dma1;			/* Offset 0x0038 */
+	uint8_t enable_i2_c0;			/* Offset 0x0039 */
+	uint8_t enable_i2_c1;			/* Offset 0x003a */
+	uint8_t enable_i2_c2;			/* Offset 0x003b */
+	uint8_t enable_i2_c3;			/* Offset 0x003c */
+	uint8_t enable_i2_c4;			/* Offset 0x003d */
+	uint8_t enable_i2_c5;			/* Offset 0x003e */
+	uint8_t enable_i2_c6;			/* Offset 0x003f */
+	uint8_t enable_pwm0;			/* Offset 0x0040 */
+	uint8_t enable_pwm1;			/* Offset 0x0041 */
+	uint8_t enable_hsi;			/* Offset 0x0042 */
+	uint8_t igd_dvmt50_pre_alloc;		/* Offset 0x0043 */
+	uint8_t aperture_size;			/* Offset 0x0044 */
+	uint8_t gtt_size;			/* Offset 0x0045 */
+	uint32_t serial_debug_port_address;	/* Offset 0x0046 */
+	uint8_t serial_debug_port_type;		/* Offset 0x004a */
+	uint8_t mrc_debug_msg;			/* Offset 0x004b */
+	uint8_t isp_enable;			/* Offset 0x004c */
+	uint8_t scc_enable_pci_mode;		/* Offset 0x004d */
+	uint8_t igd_render_standby;		/* Offset 0x004e */
+	uint8_t txe_uma_enable;			/* Offset 0x004f */
+	uint8_t os_selection;			/* Offset 0x0050 */
+	uint8_t emmc45_ddr50_enabled;		/* Offset 0x0051 */
+	uint8_t emmc45_hs200_enabled;		/* Offset 0x0052 */
+	uint8_t emmc45_retune_timer_value;	/* Offset 0x0053 */
+	uint8_t unused_upd_space1[156];		/* Offset 0x0054 */
+	struct memory_down_data memory_params;	/* Offset 0x00f0 */
+	uint16_t terminator;			/* Offset 0x0100 */
+};
+
+#define VPD_IMAGE_ID		0x3157454956594C56	/* 'VLYVIEW1' */
+#define VPD_IMAGE_REV		0x00000303
+
+struct __packed vpd_region {
+	uint64_t sign;				/* Offset 0x0000 */
+	uint32_t img_rev;			/* Offset 0x0008 */
+	uint32_t upd_offset;			/* Offset 0x000c */
+	uint8_t unused[16];			/* Offset 0x0010 */
+	uint32_t fsp_res_memlen;		/* Offset 0x0020 */
+	uint8_t platform_type;			/* Offset 0x0024 */
+	uint8_t enable_secure_boot;		/* Offset 0x0025 */
+};
+#endif
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h
new file mode 100644
index 0000000..ab4e059
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -0,0 +1,13 @@ 
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_GPIO_H_
+#define _X86_ARCH_GPIO_H_
+
+/* Where in config space is the register that points to the GPIO registers? */
+#define PCI_CFG_GPIOBASE 0x44
+
+#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/board/intel/minnowmax/Kconfig b/board/intel/minnowmax/Kconfig
new file mode 100644
index 0000000..d9e370a
--- /dev/null
+++ b/board/intel/minnowmax/Kconfig
@@ -0,0 +1,30 @@ 
+if TARGET_MINNOWMAX
+
+config SYS_BOARD
+	default "minnowmax"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "baytrail"
+
+config SYS_CONFIG_NAME
+	default "minnowmax"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select INTEL_BAYTRAIL
+	select BOARD_ROMSIZE_KB_8192
+
+config PCIE_ECAM_BASE
+	default 0xe0000000
+
+config DEBUG_UART_BASE
+	default 0x3f8
+
+config DEBUG_UART_CLOCK
+	default 1843200
+
+endif
diff --git a/board/intel/minnowmax/MAINTAINERS b/board/intel/minnowmax/MAINTAINERS
new file mode 100644
index 0000000..d655761
--- /dev/null
+++ b/board/intel/minnowmax/MAINTAINERS
@@ -0,0 +1,6 @@ 
+CircuitCo Minnowboard Max
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/intel/minnowmax
+F:	include/configs/minnowmax.h
+F:	configs/minnowmax_defconfig
diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile
new file mode 100644
index 0000000..1a61432
--- /dev/null
+++ b/board/intel/minnowmax/Makefile
@@ -0,0 +1,7 @@ 
+#
+# Copyright (C) 2015, Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= minnowmax.o start.o
diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c
new file mode 100644
index 0000000..6e82b16
--- /dev/null
+++ b/board/intel/minnowmax/minnowmax.c
@@ -0,0 +1,32 @@ 
+/*
+ * Copyright (C) 2015, Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ibmpc.h>
+#include <asm/pnp_def.h>
+#include <netdev.h>
+#include <smsc_lpc47m.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, 4)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
+
+	return 0;
+}
+
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
+{
+	return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/board/intel/minnowmax/start.S b/board/intel/minnowmax/start.S
new file mode 100644
index 0000000..2c941a4
--- /dev/null
+++ b/board/intel/minnowmax/start.S
@@ -0,0 +1,9 @@ 
+/*
+ * Copyright (C) 2015, Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+	jmp	early_board_init_ret
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
new file mode 100644
index 0000000..7bc9085
--- /dev/null
+++ b/configs/minnowmax_defconfig
@@ -0,0 +1,13 @@ 
+CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
+CONFIG_X86=y
+CONFIG_TARGET_MINNOWMAX=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_SEPARATE=y
+CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
+CONFIG_VIDEO_X86=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_DEBUG_UART_NS16550=y
+CONFIG_DEBUG_UART=y
+CONFIG_MMCONF_BASE_ADDRESS=0xe0000000
+CONFIG_HAVE_INTEL_ME=y
diff --git a/doc/README.x86 b/doc/README.x86
index a9105f8..c699b79 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -18,11 +18,11 @@  U-Boot supports running as a coreboot [1] payload on x86. So far only Link
 on other x86 boards since coreboot deals with most of the low-level details.
 
 U-Boot also supports booting directly from x86 reset vector without coreboot,
-aka raw support or bare support. Currently Link and Intel Crown Bay board
-support running U-Boot 'bare metal'.
+aka raw support or bare support. Currently Link, Intel Crown Bay and Intel
+Minnowboard Max support running U-Boot 'bare metal'.
 
-As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux
-kernel as part of a FIT image. It also supports a compressed zImage.
+As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
+Linux kernel as part of a FIT image. It also supports a compressed zImage.
 
 Build Instructions
 ------------------
@@ -47,7 +47,7 @@  Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
 to point to a new board. You can also change the Cache-As-RAM (CAR) related
 settings here if the default values do not fit your new board.
 
-Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
+Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
 little bit tricky, as generally it requires several binary blobs which are not
 shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
 not turned on by default in the U-Boot source tree. Firstly, you need turn it
@@ -110,6 +110,33 @@  Now you can build U-Boot and obtain u-boot.rom
 $ make crownbay_defconfig
 $ make all
 
+
+Intel Minnowboard Max instructions:
+
+This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
+Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
+the time of writing). Put it in the board directory:
+board/intel/minnowmax/fsp.bin
+
+Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
+directory: board/intel/minnowmax/vga.bin
+
+You still need two more binary blobs. These come from the sample SPI image
+provided in the FSP (SPI.bin at the time of writing).
+
+Use ifdtool in the U-Boot tools directory to extract the images from that
+file, for example:
+
+   $ ./tools/ifdtool -x BayleyBay/SPI.bin
+   $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin
+   $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
+
+Now you can build U-Boot and obtain u-boot.rom
+
+$ make minnowmax_defconfig
+$ make all
+
+
 Test with coreboot
 ------------------
 For testing U-Boot as the coreboot payload, there are things that need be paid
@@ -130,6 +157,16 @@  symbol address of _start (in arch/x86/cpu/start.S).
 If you want to use ELF as the coreboot payload, change U-Boot configuration to
 use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
 
+To enable video you must enable these options in coreboot:
+
+   - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
+   - Keep VESA framebuffer
+
+At present it seems that for Minnowboard Max, coreboot does not pass through
+the video information correctly (it always says the resolution is 0x0). This
+works correctly for link though.
+
+
 CPU Microcode
 -------------
 Modern CPUs usually require a special bit stream called microcode [5] to be
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
new file mode 100644
index 0000000..823e051
--- /dev/null
+++ b/include/configs/minnowmax.h
@@ -0,0 +1,72 @@ 
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_X86_SERIAL
+#define CONFIG_SMSC_LPC47M
+
+#define CONFIG_PCI_MEM_BUS		0xd0000000
+#define CONFIG_PCI_MEM_PHYS		CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE		0x10000000
+
+#define CONFIG_PCI_PREF_BUS		0xc0000000
+#define CONFIG_PCI_PREF_PHYS		CONFIG_PCI_PREF_BUS
+#define CONFIG_PCI_PREF_SIZE		0x10000000
+
+#define CONFIG_PCI_IO_BUS		0x2000
+#define CONFIG_PCI_IO_PHYS		CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE		0xe000
+
+#define CONFIG_SYS_EARLY_PCI_INIT
+#define CONFIG_PCI_PNP
+#define CONFIG_RTL8169
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \
+					"stdout=vga,serial\0" \
+					"stderr=vga,serial\0"
+
+#define CONFIG_SCSI_DEV_LIST            \
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
+#define CONFIG_SPI_FLASH_SST
+
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_CMD_MMC
+
+#undef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT		1
+
+#define CONFIG_X86_OPTION_ROM_FILE		vga.bin
+#define CONFIG_X86_OPTION_ROM_ADDR		0xfff90000
+
+#ifndef CONFIG_SYS_COREBOOT
+#define CONFIG_VIDEO_VESA
+#endif
+#define VIDEO_IO_OFFSET				0
+#define CONFIG_X86EMU_RAW_IO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+
+#define CONFIG_FIT_SIGNATURE
+#define CONFIG_RSA
+
+/* Avoid a warning in the Realtek Ethernet driver */
+#define CONFIG_SYS_CACHELINE_SIZE 16
+
+#endif	/* __CONFIG_H */