@@ -118,7 +118,7 @@ static void tc1796_initfn(Object *obj)
{
TriCoreCPU *cpu = TRICORE_CPU(obj);
- set_feature(&cpu->env, TRICORE_FEATURE_13);
+ set_feature(&cpu->env, TRICORE_FEATURE_131);
}
static void aurix_initfn(Object *obj)
@@ -255,6 +255,7 @@ target_ulong helper_mul_suov(CPUTriCoreState *env, target_ulong r1,
int64_t t1 = extract64(r1, 0, 32);
int64_t t2 = extract64(r2, 0, 32);
int64_t result = t1 * t2;
+
return suov32(env, result);
}
@@ -745,7 +745,7 @@ static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
tcg_gen_and_tl(temp, temp, mask);
tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
/* write back result */
- tcg_gen_movcond_tl(cond, r3, r4, t0, result, r3);
+ tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
tcg_temp_free(t0);
tcg_temp_free(temp);
@@ -3898,7 +3898,7 @@ static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_RCR_SEL:
temp = tcg_const_i32(0);
temp2 = tcg_const_i32(const9);
- tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r4], temp,
+ tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], temp2);
tcg_temp_free(temp);
tcg_temp_free(temp2);
@@ -3906,7 +3906,7 @@ static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_RCR_SELN:
temp = tcg_const_i32(0);
temp2 = tcg_const_i32(const9);
- tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r4], temp,
+ tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], temp2);
tcg_temp_free(temp);
tcg_temp_free(temp2);
Fix tc1796 cpu model using wrong ISA version. Fix cond_add sometimes writing back wrong result. Fix RCR_SEL and RCR_SELN using wrong registers for result and cond. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> --- target-tricore/cpu.c | 2 +- target-tricore/op_helper.c | 1 + target-tricore/translate.c | 6 +++--- 3 files changed, 5 insertions(+), 4 deletions(-)